ICE1CS02G Infineon Technologies, ICE1CS02G Datasheet - Page 13

no-image

ICE1CS02G

Manufacturer Part Number
ICE1CS02G
Description
IC PFC CTRLR AVERAGE CURR DSO16
Manufacturer
Infineon Technologies
Datasheet

Specifications of ICE1CS02G

Mode
Average Current
Frequency - Switching
65kHz
Current - Startup
1.3mA
Voltage - Supply
11 V ~ 25 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SP000444092
SP000783614

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ICE1CS02G
Manufacturer:
POWERSEM
Quantity:
201
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ICE1CS02G
Manufacturer:
INFINEON
Quantity:
101
Price:
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
V
objective.
Figure 13
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 1 (PFC
ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T
kept discharged. The ramp is then allowed to rise after
T
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
Figure 15 shows the timing diagrams of T
PWM waveforms.
Figure 14
3.4.11
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin 4 (PFC VCOMP). This block has been
Version 1.0
GATE
drive
OFFMIN
IN
V
V
PWM
. Figure 14 shows the scheme to achieve the
(1)
CREF
RAMP
V
CREF
(1)
expires. The off time of the boost transistor
is a function of V
ramp profile
Nonlinear Gain Block
Average Current Control in CCM
Ramp and PWM waveforms
400ns
OFFMIN
OFF
, and thus to the input voltage
OFF
T
(400ns typ.) and the ramp is
OFFMIN
.
ICOMP
PWM cycle
ave(I
released
ramp
IN
) at ICOMP
OFFMIN
and the
t
t
13
designed to support the wide input voltage range (85-
265VAC).
3.4.12
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T
are designed to meet a maximum duty cycle D
95% at the GATE output under 65kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 16.
Figure 15
3.4.13
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
sensing voltage at VSENSE which is a resistive divider
tapping from V
OTA1 which has an internal reference of 3V. Figure 17
shows the important blocks of this voltage loop.
3.4.14
The compensation of the voltage loop is installed at the
pin 4 (PFC VCOMP) (see Figure 17). This is the output
of OTA1 and the compensation must be connected at
this pin to ground. The compensation is also
responsible for the soft start function which controls an
increasing AC input current during start-up.
PWM on signal
Current Loop
Peak Current
Toffmin
400ns
OUT
Voltage Loop Compensation
Combi PFC/ PWM Controller
Limit
PWM Logic
Voltage Loop
PWM Logic
. This loop is closed by the feedback
OUT
. The pin VSENSE is the input of
Limit Latch
Current
PWM on
Functional Description
R
S
Latch
S
R
L1
L2
Q
Q
G1
ICE1CS02
25 July 2008
turn GATE on
HIGH =
OFFMIN
MAX
of
,

Related parts for ICE1CS02G