ISL6271ACRZ Intersil, ISL6271ACRZ Datasheet
ISL6271ACRZ
Specifications of ISL6271ACRZ
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ISL6271ACRZ Summary of contents
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... ISL6271 Evaluation Kit” Ordering Information 16 LVCC 15 PART NUMBER* ISL6271ACR 14 VPLL ISL6271ACRZ (Note) VSRAM *Add “-T” suffix for tape and reel. VOUT 11 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate ...
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Regulator Block Diagram LVCC EN PVCC SCL (VID SDA (VID 1) STATIC VID2 VID VID3 LOGIC VIDEN Functional Block Diagram PGOOD VIDEN SCL/VID0 SDA/VID1 VID2 OV VID3 UV VOUT DAC EN SOFT ERROR AMP ...
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Absolute Maximum Ratings (PVCC, VCC, LVCC) to GND .7V PHASE to PGND . ...
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Electrical Specifications Operating Conditions, Unless Otherwise Noted shown in Figure 19, Typical Application Circuit: Vout = 1.6V, I PARAMETER Output Tolerance Maximum Average Output Current Current Limit Line Regulation Load Regulation Undervoltage Threshold Start-Up Time SYSTEM Supply Current ...
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... Typical Operating Performance Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made 4.7µH drumcore with 100mΩ of DCR and an output capacitance of 10µF. X5R; Rcomp = 50kΩ, Vin = 3.6V unless otherwise noted. 1.094 1.093 1.092 1 ...
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... Typical Operating Performance Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made 4.7µH drumcore with 100mΩ of DCR and an output capacitance of 10µF. X5R; Rcomp = 50kΩ, Vin = 3.6V unless otherwise noted. DATA CLK Vout = 0.85 to 1.6V 5mV/µs, 40µs/DIV 2 FIGURE 8 ...
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... Typical Operating Performance Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made 4.7µH drumcore with 100mΩ of DCR and an output capacitance of 10µF. X5R; Rcomp = 50kΩ, Vin = 3.6V unless otherwise noted. VOUT PGOOD PHASE Forced PGOOD fault ...
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... VID pins. The slew rate is always fixed by the soft-start capacitor. Core Regulator Output The ISL6271A core regulator is a synchronous buck regulator that employs an Intersil proprietary switch-mode topology known as Synthetic Ripple Regulation (SRR). The SRR architecture is a derivative of the conventional hysteretic-mode regulator without the inherent noise sensitivities and dependence on output capacitance ESR ...
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TABLE 2. SLEW RATE-SET BIT DATA BYTE Soft-Start and Slew Rate ...
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BBAT The BBAT pin is an input voltage to the ISL6271A that supports the BFLT# indicator function as described above. When the main battery is absent inadequate potential, the BBAT input voltage supplies power to support the BFLT# ...
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I C SEND BYTE PROTOCOL START SLAVE ADDRESS COMMAND BYTE RECEIVE BYTE PROTCOL S 0 ...
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... To minimize ripple current and preserve transient response, Intersil recommends an output inductor between 3.3µH and 4.7µH. Higher values of inductance will minimize the risk of tripling the over-current minimum threshold of 950mA. ...
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Light Load Operation - DCM A light load is defined when the output inductor ripple current reaches zero before the next switching cycle. Under this condition, the ISL6271A synchronous rectifier will turn off emulating a diode to prevent negative inductor ...
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... SRAM power domains and should be connected to the ISL6271A enable pin. The SYS_EN pin is responsible for enabling the system regulator. Figure 25 illustrates one possible configuration using the Intersil EL7536 to power five of the 10 domains. NOTE: Intel warns that an improper power sequence can damage the processor ...
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... ISL6292 data sheet - Battery Charger [2] EL7536 data sheet - System regulator BFLT# [3] C-Code examples for PWR_I2C bus communication - Intersil support documentation available upon request. [4] PHILLIPS I [5] http://www.semiconductors.philips.com/buses/i2c/ [6] Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for MLF Packages” ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...