PM6670AS STMicroelectronics, PM6670AS Datasheet
PM6670AS
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PM6670AS Summary of contents
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... Table 1. Device summary Order codes PM6670AS PM6670ASTR February 2010 Description The device PM6670AS is a complete DDR2/3 power supply regulator designed to meet JEDEC specifications. It integrates a constant on-time (COT) buck controller Apk sink/source low drop out regulator and low noise buffered reference. The COT architecture assures fast transient response supporting both electrolytic and ceramic output capacitors ...
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... Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 VDDQ output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Over voltage and under voltage protections . . . . . . . . . . . . . . . . . . . . . 35 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 VTT and VTTREF soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VTTREF and VTT outputs discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 14436 Rev 2 PM6670AS ...
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... PM6670AS 7.3 S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 All ceramic capacitors application ...
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... LGATE PM6670AS PM6670A PM6670A 19 19 CSNS CSNS VTTSNS VTTSNS 16 16 VTT VTT PGND PGND 9 9 VTTGND VTTGND VSNS VSNS BYP BYP BYP Doc ID 14436 Rev BOOT BOOT LIM LIM LIM PM6670AS VIN VIN VDDQ VDDQ OUT OUT OUT INT INT INT ...
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... Connections Figure 2. Pin connection (through top view) VTTGND VTTGND VTTGND VTTSNS VTTSNS VTTSNS DDRSEL DDRSEL DDRSEL VTTREF VTTREF VTTREF PM6670A PM6670A PM6670A PM6670A PM6675S PM6670AS SGND SGND SGND AVCC AVCC AVCC Doc ID 14436 Rev 2 Pin settings VCC VCC VCC LGATE ...
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... See Power Management Pins section for details. S3 pin can't be left floating. Power-Good signal (open drain output). High when VDDQ output voltage is within ±10% of nominal value. Power ground for the switching section. Low-side gate driver output. Doc ID 14436 Rev 2 PM6670AS Function ...
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... PM6670AS Table 2. Pin functions (continued) N° Pin 18 VCC 19 CSNS 20 PHASE 21 HGATE 22 BOOT 23 LDOIN 24 VTT +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND. Current Sense Input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSon sensing) Switch node connection and return path for the high-side gate driver ...
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... VTTREF, VREF, VTT, VTTSNS to SGND LDOIN, VTT, VTTREF, LDOIN to VTTGND Power dissipation @ °C A Parameter Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range Parameter Doc ID 14436 Rev 2 PM6670AS Value Unit -0 -0 -0.3 to 0 +0.3 VCC -0 ...
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... PM6670AS 4 Electrical characteristics T = -25 ° °C, VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not A otherwise specified Table 6. Electrical characteristics Symbol Parameter Supply section I Operating current IN I Operating current in STR STR Operating current shutdown AVCC under voltage lockout upper threshold UVLO ...
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... AVCC, no load Rsense = 1 kΩ PGND CSNS HGATE high state (pull-up) HGATE low state (pull-down) LGATE high state (pull-up) LGATE low state (pull-down) PG forced PG,SINK Doc ID 14436 Rev 2 PM6670AS Min Typ Max Unit 1.5 V 1.8 -1.5 1.5 % μA 110 120 130 ...
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... PM6670AS Table 6. Electrical characteristics (continued) Symbol Parameter VTTREF discharge resistance in non-tracking discharge mode VDDQ Output threshold synchronous for final tracking to non-tracking discharge transition V LDO section TT LDO input bias current in full- I LDOIN,ON on state I LDO input bias current in LDOIN, suspend-to-RAM state STR I LDO input bias current in ...
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... I OSC, VOSC input leakage current LEAK Thermal shutdown T Shutdown temperature SHDN 1. Guaranteed by design. Not production tested 12/53 Test condition S3 MODE, DDRSEL and DSCG = 5 V VOSC = 500 mV (1) Doc ID 14436 Rev 2 PM6670AS Min Typ Max Unit 0.4 1 AVCC 0 AVCC 1 AVCC 0.8 ...
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... PM6670AS 5 Typical operating characteristics Figure 3. Efficiency vs load - 1.5 V and 1.8 V, Vin = 12 V 100 0.001 0.01 0.1 Output current (A) Figure 5. Switching frequency vs input voltage, 1.8 V 500 450 400 350 300 250 200 150 0.0 5.0 10.0 15.0 Input voltage (V) Figure 7. VDDQ line regulation, 1 ...
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... Figure 12. VTT load regulation, 0.790 0.780 0.770 0.760 0.750 0.740 0.730 0.5 1.5 2.5 -2.5 Figure 14. No-audible pulse-skip waveforms Doc ID 14436 Rev 2 PM6670AS 1.5 V, Vin = 12 V Forced PWM No-Audible P-S Pulse-Skip 0.01 0.1 1 Output current (A) 0.75 V, LDOIN = 1.5 V -1.5 -0.5 0.5 1.5 ...
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... PM6670AS Figure 15. Power-up sequence - AVCC above UVLO Figure 17 1.8 A VTT load transient, 0.9 V Typical operating characteristics Figure 16. VDDQ soft-start, 1.8 V, heavy load Figure 18 VTTREF load transient, 0.9 V Doc ID 14436 Rev 2 15/53 ...
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... Typical operating characteristics Figure 19. Non-tracking (soft) discharge Figure 21 VDDQ load transient, PWM 16/53 Figure 20. Tracking (fast) discharge, LDOIN = VDDQ Figure 22 VDDQ load transient, PWM Doc ID 14436 Rev 2 PM6670AS ...
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... PM6670AS Figure 23. Over-voltage protection, VDDQ = 1.8 V Typical operating characteristics Figure 24. Under-voltage protection, VDDQ = 1.8 V Doc ID 14436 Rev 2 17/53 ...
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... Current Limit Current Limit Current Limit VREF VREF VREF VREF COMP COMP COMP COMP % % % % Vr +10 Vr +10 Vr + -10 Vr -10 Vr -10 Vr -10 VSNS VSNS VSNS VSNS DDR3 DDR3 DDR3 DDR3 NTD NTD NTD NTD adj adj adj adj fix fix fix fix PM6670AS ...
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... PM6670AS 7 Device description The PM6670AS is designed to satisfy DDR2-3 power supply requirements combining a synchronous buck controller buffered reference and a high-current low-drop out (LDO) linear regulator capable of sourcing and sinking Apk. The switching controller section is a high-performance, pseudo-fixed frequency, constant-on-time (COT) based regulator specifically designed for handling fast load transient over a wide range of input voltages ...
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... VDDQ section - constant on-time PWM controller The PM6670AS uses a pseudo-fixed frequency, constant on-time (COT) controller as the core of the switching section well known that the COT controller uses a relatively simple algorithm and uses the ripple voltage derived across the output capacitor’s ESR to trigger the on-time one-shot generator. In this way, the output capacitor’ ...
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... MOSFETs' on-resistance and inductor's DCR) introduce voltage drops responsible for slight dependence on load current. In addition, the internal delay is due to a small dependence on input voltage. The PM6670AS switching frequency can be set by an external divider connected to the VOSC pin. V ...
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... Figure 28 shows the simplified block diagram of the constant-on-time controller. The switching regulator of the PM6670AS owns a one-shot generator that ignites the high- side MOSFET when the following conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.9 V), the synchronous rectifier current is below the current limit threshold and the minimum off-time has expired ...
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... PM6670AS Figure 28. Switching section simplified block diagram 7.1.2 Output ripple compensation and loop stability The loop is closed connecting the center tap of the output divider (internally, when the fixed output voltage is chosen, or externally, using the MODE pin in the adjustable output voltage mode). The feedback node is the negative input of the error comparator, while the positive input is internally connected to the reference voltage ( ...
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... COMP C C FILT FILT Δ INT INT INT INT R R INT INT t VSNS ESR ESR C C OUT OUT > ⋅ Zout ⋅ π 2 Doc ID 14436 Rev REF REF I=g (V -Vr PWM Comparator Fb1 Fb1 Fb2 Fb2 k ⋅ C ESR out PM6670AS ...
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... PM6670AS Equation 7 where μs is the integrator trans conductance. In order to ensure stability it must be also verified that: Equation 8 If the ripple on the COMP pin is greater than the integrator 150 mV, the auxiliary capacitor C can be added the desired attenuation factor of the output ripple, C FILT by: ...
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... In order to ensure stability it must be verified INT g > INT ⋅ π ⋅ π out Doc ID 14436 Rev REF REF I=g (V -Vr PWM PWM Comparator Comparator FILT FILT + R R Fb1 Fb1 Fb2 Fb2 − ESR is the total ripple at the T node, chosen Vr ⋅ Vout ⋅ R TOT PM6670AS ...
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... PM6670AS Equation 14 Moreover, the C INT Equation 15 where R is the sum of the ESR of the output capacitor and the equivalent ESR given by TOT the Virtual-ESR Network (R determines the minimum integrator capacitor value C Equation 16 The capacitor of the Virtual-ESR Network chosen as follows: Equation 17 and R is calculated to provide the desired triangular ripple voltage: ...
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... Pulse-skip and no-audible pulse-skip modes High efficiency at light load conditions is achieved by PM6670AS entering the pulse-skip mode (if enabled). When one of the two fixed output voltages is set, pulse-skip power saving is a default feature. At light load conditions the zero-crossing comparator truncates the low- side switch on-time as soon as the inductor current becomes negative ...
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... The PM6670AS has been designed to satisfy the widest range of applications involving DDR2/3 memories, SSTL15-18 buses termination and I/O supplies for CPU/Chipset. The device is provided with multilevel pins which allow the user to choose the appropriate configuration. The MODE pin is used to firstly decide between fixed preset or adjustable (user defined) output voltages ...
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... Device description When the MODE pin is connected the PM6670AS allows setting the VDDQ voltage to 1 1.5 V just forcing the DDRSEL multilevel pin ground respectively (see Figure 33 a). In this condition the pulse-skip feature is enabled. This device configuration is suitable for standard DDR2/3 memory supply applications avoiding the need for an external, high accuracy, divider for output voltage setting ...
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... DC output current plus half of the inductor ripple current: Equation 22 The PM6670AS provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced-PWM (3 quadrant working conditions). This negative current limit threshold is measured between PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal 120 mV fixed threshold ...
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... Device description The soft-start allows a gradual increase of the internal current limit threshold during start-up reducing the input/output surge currents. At the beginning of start-up, the PM6670AS current limit is set to 25% of nominal value and the under voltage protection is disabled. Then, the current limit threshold is sequentially brought to 100% in four steps of approximately 750 μ ...
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... S5 tied to GND) and DSCG pin has been properly set. Figure 37. DSCG pin connection for discharge mode selection The PM6670AS allows the user to choose between fast discharge (tracking discharge), soft discharge (non-tracking discharge discharge modes. Voltage on DSCG multilevel pin determines discharge mode as shown in Table 9 ...
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... PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through VCC and PGND pins. An important feature of the PM6670AS gate drivers is the adaptive anti-cross-conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time ...
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... Device thermal protection The internal control circuitry of the PM6670AS self-monitors the junction temperature and turns all outputs off when the 150 °C limit has been overrun. This event causes the switching section to be immediately disabled and both switches to be opened. The controller enters in soft-end Mode and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400 mV ...
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... Device description 7.2 VTTREF buffered reference and VTT LDO section The PM6670AS provides the required DDR2/3 reference voltage on the VTTREF pin. The internal buffer tracks half the voltage on the VSNS pin and has a sink and source capability mA. Higher currents rapidly deteriorate the output accuracy 100 nF (33 nF typ.) bypass capacitor to SGND is required for stability ...
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... S5 system states by connecting S3-S5 pins to their respective sleep-mode signals in the notebook's motherboard. Keeping S3 and S5 high, the S0 (Full-On) state is decoded and the outputs are alive state ( 0), the PM6670AS maintains VDDQ and VTTREF outputs active and VTT output in high-impedance as needed. In S4/S5 states ( all outputs are turned off and, according to DSCG pin voltage, the proper soft-end is performed ...
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... The following paragraphs will guide the user into a step-by-step design. 8.1 External components selection The PM6670AS uses a pseudo-fixed frequency, constant on-time (COT) controller as the core of the switching section. The switching frequency can be set by connecting an external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8 V and lower than order to ensure system's linearity ...
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... PM6670AS where Equation 27a Equation 27b Referring to the typical application schematic (figure in cover page and expression is then: Equation 28 The switching frequency directly affects two parameters: ● Inductor size: greater frequencies mean smaller inductances. In most of the applications, real estate solutions (i.e. low-profile power inductors) are mandatory also with high saturation and r.m.s. currents. ● ...
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... OUT OUT L Δ ⋅ fsw the input voltage − Δ MAX OUT ⋅ OUT MAX ⋅ fsw MAX Δ MAX RMS LOAD , MAX 12 L,RMS Δ MAX PEAK LOAD , MAX 2 Doc ID 14436 Rev 2 PM6670AS is the output voltage and OUT order to assure thermal ...
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... PM6670AS The saturation current of the inductor should be greater than I saturation core inductors. Using soft-ferrite cores it is possible (but not advisable) to push the inductor working near its saturation current. In Table 13 some inductors are listed. Table 13. Evaluated inductors (@fsw = 400 kHz) Manufacturer COILCRAFT ...
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... Equation 37 42/53 Table 14 Capacitance (μF) Rated voltage (V) Series ≤ RIPPLE , MAX ESR Δ MAX 1 > ⋅ π 2 ESR Doc ID 14436 Rev 2 PM6670AS some MLCC suitable for most of Maximum Irms @100 kHz ( 2.2 35 2.2 35 2.5 25 ⋅ C out ...
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... PM6670AS If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance could be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load load condition. ...
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... Doc ID 14436 Rev 2 Δ I ⋅ + ⋅ (max LOAD greater efficiency is achieved with gate ) must be BRDSS . Gate charge Rated reverse (nC conduction ⎞ V ⎟ ⋅ 2 OUT I ⎟ LOAD , MAX V ⎠ MAX as possible. When the high-side DSon where GS − C RSS PM6670AS ⋅ f off sw voltage ( ...
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... PM6670AS Tested low-side MOSFETs are listed in Table 17. Evaluated low-side MOSFETs Manufacturer ST STS12NH3LL ST STS25NH3LL IR Dual N-MOS can be used in applications with lower output current. Table 18 shows some suitable dual MOSFETs for applications requiring about 3 A. Table 18. Suitable dual MOSFETs Manufacturer ST STS8DNH3LL IR 8.1.5 Diode selection A rectifier across the synchronous switch is recommended ...
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... Lvalley LOAD Inductor current Inductor current MAX LOAD 2 Valley current limit is: CSNS R DSon = R CSNS 100 120 = I NEG R Doc ID 14436 Rev 2 is: Δ I − Figure 39 : Time (max) over all the input voltage LOAD ⋅ I Lvalley uA calculation (typically +0.4%/°C). DSon mV DSon PM6670AS ...
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... PM6670AS 8.1.7 All ceramic capacitors application Design of external feedback network depends on the output voltage ripple across the output capacitors' ESR. If the ripple is great enough (at least 20 mV), the compensation network simply consists Figure 40. Integrative compensation COMP C FILT The stability of the system depends firstly on the output capacitor zero frequency. It must be ...
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... The cutoff frequency INT ⋅ π CUT C and C are unnecessary. INT filt . PWM Comparator + - VREF Doc ID 14436 Rev 2 ⋅ − INT must be much CUT 1 ⋅ INT FILT + C INT FILT INT C R INT + 0.9V C FILT Integrator PM6670AS that, together VDDQ ...
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... PM6670AS Select C as shown: Equation 52 Then calculate R in order to have enough ripple voltage on the integrator input: Equation 53 Where R is the new virtual output capacitor ESR. A good trade-off is to consider an VESR equivalent ESR of 30-50 mΩ, even though the choice depends on inductor current ripple. ...
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... VFQFPN-24 4mm x 4mm mechanical data Dim θ 50/53 mm. Min Typ 0.80 0.90 0.0 0.65 4.00 3.75 4.00 3.75 0.24 0.42 0.50 24.00 6.00 6.00 0.30 0.40 0.18 2.40 2.40 Doc ID 14436 Rev 2 PM6670AS ® Max 1.00 0.05 0.80 12° 0.60 0.50 0.30 2.70 2.70 ...
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... PM6670AS Figure 42. Package dimensions Doc ID 14436 Rev 2 Package mechanical data 51/53 ...
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... Revision history 10 Revision history Table 21. Document revision history Date 14-Feb-2008 17-Feb-2010 52/53 Revision 1 Initial release. Updated: Coverpage, 2 Table 8 Doc ID 14436 Rev 2 Changes Table 2, Table 6, Section 7.1, Figure 28 PM6670AS and ...
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... PM6670AS Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...