MC34704AEP Freescale Semiconductor, MC34704AEP Datasheet - Page 31

• Manufacturer Part Number: MC34704AEP
• Description: IC POWER MANAGEMENT 56-QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC34704AEP

• Applications: Processor
• Current - Supply: 86mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Output Voltage: 5 V
• Input Voltage: 2.7 V to 5.5 V
• Switching Frequency: 750 KHz to 2 MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

processor decision to either shutoff or not, in the mean time
the control loop will try to fix itself.
implemented.
I
address $54 to access all user registers and program all
regulators features independently. Physical address is in a 7-
bit format. The extra bit to complete the 8-bit indicates the
USER PROGRAMMABLE REGISTERS
GrpC/E power sequencing setting (34704A Only)
sequence options for the GrpC/E supply (REG5), high
voltage supply (REG6), and negative voltage supply (REG7).
For 3 of the sequencing options, REG5 supply is controlled
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
C USER INTERFACE
Start Bit
OPTION
(Default)
To avoid erroneous conditions, a 20 μs filter will be
The 34704 communicates via I
The microprocessor can choose one of several voltage
Start Bit
1
7 bit Physical Address +
7 bit Physical Address +
7 bit Physical ADD +
1 0 1 0 1 0 0
MSB
1010100 + 0
1 0 1 0 1
0
1010100 + 0
1010100 + 0
(w) bit
(w) bit
(w) bit
LSB
0
ACK
2
ACK
0 0 0
C using a default device
0
REG6 and REG7 ramp up together.
1 0 0 0 0 0 0
REG5 is independently controlled
LOGIC COMMANDS AND REGISTERS
Figure 8. Reading sequence I
Sub-address
Figure 7. Writing sequence I
1XXXXXXX
ACK
GRPC/E ENABLED
(MSB=1)
ACK
ACK
0
0
0 0 0 0 0 0 1
ACK
ACK
Sub-Address
Sub-Address
0XXXXXXX
0XXXXXXX
0
(MSB=0)
(MSB=0)
RS
RS
1
DVSSTAT flag is asserted “Done”.
soft start is done, the OV/UV protection is masked from
reporting that the output is in regulation.
reading or writing mode as shown in
After each byte read or sent, the MC34704 answers with an
Acknowledge bit, indicating the bite was transferred
successfully.
and tied with REG6 and REG7 in a preset power sequence.
By default, only REG6 and REG7 are involved in the power
sequence and REG5 is independently controlled with GrpE.
sequencing options (CCDSEQ[1:0]). These bits value is
latched in at GrpC power up and will not be allowed to change
unless a power recycle happens.
1 0 1 0 1 0 0
The OV/UV fault flag is masked during DVS until
To keep the RST output low during ramp up and until the
34704A assigns 2 bits to program the GrpC/E power
2
2
C bit stream
1010100 + 1
ADD + (r) bit
C bit stream
0
Physical
ACK
ACK
ACK
0 0 0 0 1 1 1 1
0
0
REG6 and REG7 ramp down together
REG5 is independently controlled
ACK
ACK
XXXXXXXX
XXXXXXXX
LOGIC COMMANDS AND REGISTERS
0
0 0 0 1 1 1 1 1
GRPC/E DISABLED
FUNCTIONAL DEVICE OPERATION
Data
Data
Data Read
XXXXXXX
Figure 7
ACK
ACK
ACK
ACK End Bit
and
0
0
End Bit
ACK
1
Figure
34704
8.
31