LTC2926IUFD#TRPBF Linear Technology, LTC2926IUFD#TRPBF Datasheet
LTC2926IUFD#TRPBF
Specifications of LTC2926IUFD#TRPBF
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LTC2926IUFD#TRPBF Summary of contents
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... I/O ■ Microprocessor, DSP and FPGA Supplies ■ Servers ■ Communications Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 6897717. U TYPICAL APPLICATIO 1.8V MODULE IRF7413Z OUT 100Ω ...
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LTC2926 ABSOLUTE AXI U RATI GS (Notes 1, 2) Supply Voltage (V ) ................................. –0.3V to 10V CC Input Voltages ON ......................................................... –0.3V to 10V RAMP .............................................–0. TRACK1, TRACK2 ........................–0. PGTMR ........................................–0.3V to ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at T SYMBOL PARAMETER Supply Voltage V Input Supply Voltage CC I Input Supply Current CC V Input Supply Undervoltage Lockout CC(UVLO) ΔV Input Supply Undervoltage Lockout CC(UVLO) Hysteresis Control and I/O ...
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LTC2926 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at T SYMBOL PARAMETER V RAMPBUF Pin Output High Voltage RAMPBUF(OH) (V – RAMPBUF Tracking Channels Current Mismatch ERROR(%) FBn TRACKn (I – I ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS unless otherwise specifi ed. Supply Current vs Supply Voltage –3mA RAMPBUF I = –1mA 8 TRACKn I = –1mA FBn 0mA RAMPBUF I = 0mA TRACKn ...
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LTC2926 W U TYPICAL PERFOR A CE CHARACTERISTICS unless otherwise specifi ed. RAMPBUF Output Low Voltage vs Temperature 3mA RAMPBUF 2. 5. –50 – ...
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CTIO S GN/UFD Packages D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15): Remote Sense Switches #1 and #2. A 10Ω (max) switch connects each pair of pins (D1/S1 and D2/S2) ...
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LTC2926 CTIO S GN/UFD Packages RAMP (Pin 11/ Pin 9): Ramp Buffer Input. Connect the RAMP pin to the master ramp signal to force the slave supplies to track it. When the RAMP pin is ...
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CTIO AL BLOCK DIAGRA + 2.4V UVLO – DELAY – 0.6V + 0.5V DELAY – + – 1.23V + RSGATE – 4. RSGATE – 1.23V + MGATE – RAMP ...
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LTC2926 U U APPLICATIO S I FOR ATIO Power Supply Tracking and Sequencing The LTC2926 handles a variety of power-up profi les to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These require- ments fall ...
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U U APPLICATIO S I FOR ATIO SUPPLY LTC2926 V CC MASTER RAMP R TB TRACK I TRACK R TA Figure 5. Simplifi ed Tracking Cell and Gate Controller Cell Combination R and R . The slave output voltage varies ...
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LTC2926 U U APPLICATIO S I FOR ATIO SUPPLY MODULE OUT SUPPLY MODULE OUT R X1 SENSE D1 MGATE RAMP + 4.9V SGATE1 V + 4.9V CC SGATE2 ON/OFF 1.23V RAMPBUF 0.8V R TB1 TRACK1 ...
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U U APPLICATIO S I FOR ATIO 3.3V MODULE OUT SENSE 10Ω 1.8V MODULE OUT SENSE 10Ω 2.5V MODULE V IN OUT IN C MGATE R X2 ...
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LTC2926 U U APPLICATIO S I FOR ATIO Status Output The output aspect of the STATUS/PGI pin allows the LTC2926 to control and communicate with external downstream circuits. The pin is driven internally by an N-channel MOSFET pull-down to GND ...
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U U APPLICATIO S I FOR ATIO through the power good timeout period, a fault and retry will subsequently occur. To ensure a consistent power good timeout period, the LTC2926 requires the PGTMR pin voltage to fall below 0.1V for ...
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LTC2926 U U APPLICATIO S I FOR ATIO SUPPLY + V – DS MODULE Q0 OUT R X MGATE SENSE RSGATE ( – OUT ...
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U U APPLICATIO S I FOR ATIO SUPPLY MODULE V IN OUT 10Ω SENSE 10Ω SUPPLY MODULE V IN OUT IN 0.1µ MGATE X2 SENSE V MGATE RAMP SGATE1 ...
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LTC2926 U U APPLICATIO S I FOR ATIO 500mV/DIV Figure 13. Coincident Tracking Waveforms from Figure 14 Circuit before the master ramp reaches its fi nal value; otherwise, the slave supply voltage will be held below its intended level. Calculate ...
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U U APPLICATIO S I FOR ATIO have 1% tolerance. The 3-step design procedure detailed above can be used to determine component values. Only the slave 1 supply is considered here, as the procedure is the same for the slave ...
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LTC2926 U U APPLICATIO S I FOR ATIO 500mV/DIV Figure 15. Ratiometric Tracking Waveforms from Figure 16 Circuit Ratiometric Tracking Example This example converts the coincident tracking example to the ratiometric tracking profi le shown in Figure 15, using two ...
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U U APPLICATIO S I FOR ATIO 500mV/DIV Figure 17. Offset Tracking Waveforms from Figure 18 Circuit Offset Tracking Example Converting the circuit in the coincident tracking example to the offset tracking profi le shown in Figure 17 is relatively ...
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LTC2926 U U APPLICATIO S I FOR ATIO 500mV/DIV Figure 19. Supply Sequencing Waveforms from Figure 20 Circuit Supply Sequencing Example In Figure 19, the two slave supplies are sequenced using a master ramp signal the ratiometric tracking ...
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U U APPLICATIO S I FOR ATIO Slave Control Without MOSFETs The LTC2926 can control tracking and sequencing of a slave supply without a MOSFET if the supply generator’s output voltage is set by an accessible resistive voltage divider and ...
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LTC2926 U U APPLICATIO S I FOR ATIO Final Sanity Checks The collection of equations below is useful for identifying unrealizable solutions. As stated in step 3 of the design procedure, the slave supply must fi nish ramping before the ...
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U U APPLICATIO S I FOR ATIO MASTER SLAVE2 LARGE τ SLAVE1 R L 5ms/DIV Figure 24. Tracking Effects of Weak Resistive Load Under worst-case conditions, FB pin voltages may reach the maximum clamp voltage of 2.4V. ...
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LTC2926 PACKAGE DESCRIPTIO .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .0075 – .0098 (0.19 – 0.25) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE ...
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... SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UFD Package 20-Lead Plastic QFN (4mm × ...
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... Controls Three Supplies Without FETs, Includes Three Shutdown Control Pins Controls Single Supply Without FETs, Daisy-Chain for Multiple Supplies ● www.linear.com SLAVE4 SLAVE3 R FB3 R FA3 R FB4 FA4 NC 10k 10k SLAVE2 SLAVE1 R FB1 R FA1 R FB2 R FA2 NC FAULT STATUS LT 0506 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 2926fa ...