ISL8844AABZ Intersil, ISL8844AABZ Datasheet - Page 13

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ISL8844AABZ

Manufacturer Part Number
ISL8844AABZ
Description
IC PWM CTRLR SGL-ENDED 8-SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL8844AABZ

Pwm Type
Current Mode
Number Of Outputs
1
Frequency - Max
2MHz
Duty Cycle
50%
Voltage - Supply
9 V ~ 30 V
Buck
Yes
Boost
Yes
Flyback
Yes
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
Yes
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (3.9mm Width)
Frequency-max
2MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL8844AABZ
Manufacturer:
Intersil
Quantity:
500
Part Number:
ISL8844AABZ
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
ISL8844AABZ-T
Manufacturer:
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Part Number:
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0
Example:
V
V
L
Ns/Np = 10
Lp = 8.0μH
I
Switching Frequency, f
Duty Cycle, D = 28.6%
R
Solve for the current sense resistor, R
R
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 12.
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R
CT to CS.
R
Determine the new value of R
R’
Additional slope compensation may be considered for
design margin. The above discussion determines the
minimum external ramp that is required. The buffer transistor
used to create the external ramp from RTCT should have a
sufficiently high gain (>200) so as to minimize the required
base current. Whatever base current is required reduces the
charging current into RTCT and will reduce the oscillator
frequency.
O
s
IN
O
6
CS
9
CS
= 800μH
= 200mA
= 499Ω
= 2.67kΩ
= 48V
= 12V
= 295mΩ
= 350mΩ
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
sw
= 200kHz
13
CS
(R’
CS
CS
) using Equation 18.
, using Equation 15.
9
, from
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. V
bypassed directly to GND with good high frequency
capacitors.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
DD
should be
April 18, 2007
FN6320.3

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