IP1001 International Rectifier, IP1001 Datasheet - Page 12

IC PWR BLOCK SGL PHS 20A 256-BGA

IP1001

Manufacturer Part Number
IP1001
Description
IC PWR BLOCK SGL PHS 20A 256-BGA
Manufacturer
International Rectifier
Series
iPOWIR™r
Type
Step-Down (Buck)r
Datasheet

Specifications of IP1001

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.93 ~ 2 V
Current - Output
20A
Frequency - Switching
200kHz, 300kHz
Voltage - Input
3.3 ~ 12 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
256-BGA (218 bumps)
Power - Output
3.1W
For Use With
IRDCIP1001-A - CONV SGL PHA SYNC BUCK 3.3-4.5V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*IP1001

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iP1001
Application Issues
Setting V
above 2V
OUT
In certain applications where the output voltage is
required to be set higher than the maximum DAC
code setting of 2V, it is possible to use an external
resistive voltage divider which, for accuracy, needs
to have 1% or better tolerance. The switching
frequency should be set at 200kHz by connecting
the FREQ pin to V
. Also, the output voltage should
DD
never be set higher than 3.3V with a V
minimum of
IN
5V, or 2.5V with a V
minimum of 3.3V. The DAC
IN
code should be set to 2V and the following equation
used to select the resistors:
V
= V
(1 + R3/R4)
x
OUT
F
See the reference design for reference designators.
Note that the impedance at V
is 180K
±35%. It is
F
recommended that R3 be calculated assuming a
value of 1k for R4. Connect V
to V
and GNDS to
FS
F
PGND.
Duty Cycle D = V
/ V
>50%
OUT
IN
For duty cycles >50% the switching frequency should
be set at 200kHz. 300kHz switching frequency can
be selected if the output is less than 2V and the duty
cycle is <50%.
For duty cycles >50%, add external compensation
ramp from the Vsw terminal of the iP1001 device as
shown in the reference design through R9 resistor
and C21 capacitor (Fig 10a.). For optimum perfor-
mance maintain a RC time constant of approximately
5 s.
12
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