CS51413EDR8G ON Semiconductor, CS51413EDR8G Datasheet - Page 7

• Manufacturer Part Number: CS51413EDR8G
• Description: IC REG BUCK LV 1.5A SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of CS51413EDR8G

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Current - Output: 1.5A
• Frequency - Switching: 520kHz
• Voltage - Input: 4.5 ~ 40 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Style: SMD/SMT
• Primary Input Voltage: 40V
• No. Of Outputs: 1
• Output Current: 1.5A
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Current Rating: 1.5A
• Filter Terminals: SMD
• Input Voltage Primary Max: 40V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: CS51413EDR8GOS

V
control technique and provides a high level of integration to
enable high power density design optimization.
control elements such that when connected to the feedback
signal of a power converter, sufficient loop gain and
bandwidth is available to regulate the voltage set point
against line and load variations. The arrangement of these
elements differentiates a voltage mode, or a current mode
controller from a V2 device.
controller.
is compared with a reference voltage to develop an error
signal which is fed to one input of the PWM. The second
input to the PWM, however, is neither a fixed voltage ramp
nor the switch current, but rather the feedback signal from
the output of the converter. This feedback signal provides
both DC information as well as AC information (the control
ramp) for the converter to regulate its set point. The control
architecture is known as V2 since both PWM inputs are
derived from the converter’s output voltage. This is a little
misleading because the control ramp is typically generated
from current information present in the converter.
Figure 4 is processed in one of two ways before being routed
to the inputs of the PWM comparator. The Fast Feedback
path (FFB) adds slope compensation to the feedback signal
before passing it to one input of the PWM. The Slow
Feedback path (SFB) compares the original feedback signal
against a DC reference. The error signal generated at the
output of the error amplifier VC is filtered by a low
frequency pole before being routed to the second input of the
PWM. Each switch cycle is initiated (S1 on), when the
output latch is set by the oscillator. Each switch cycle
terminates (S1 off), when the FFB signal (AC plus output
DC) exceeds SFB (error DC), and the output latch is reset.
In the event of a load transient, the FFB signal changes
faster, in relation to the filtered SFB signal, causing duty
Switch
2
The CS5141X family of buck regulators utilizes a V2
Every pulse width modulated controller configures basic
Figure 3 illustrates the basic architecture of a V2
In common with V mode or I mode, the feedback signal
The feedback signal from the buck converter shown in
Control
Latch/Drive
Clock
THEORY OF OPERATION
Figure 3. V2 Control
PWM
V2 Control Ramp
Z2
Error Amplifier
V
REF
+
−
V
APPLICATIONS INFORMATION
FB
Z1
http://onsemi.com
V
O
7
cycle modulation to occur. Actual oscilloscope waveforms
taken from the converter show the switch node V
the error signal V
component only) are shown in Figure 5.
faster, in relation to the filtered SFB signal, causing duty
cycle modulation to occur. By this means the converter’s
transient response time is independent of the error amplifier
bandwidth. The error amplifier is used here to ensure
excellent DC accuracy.
ramp is required at the feedback pin.
In the event of a load transient, the FFB signal changes
In order for the controller to operate optimally, a stable
V
Buck
Controller
2
Control
Duty Cycle
V
Figure 4. Buck Converter with V2 Control
IN
PWM Com-
Latch
parator
R
S1
Oscillator
S
C
D1
and the feedback signal V
−
+
Figure 5.
Slope
Comp
+
Amplifier
L1
V
Error
FFB
C
SFB
−
+
C1
+
−
V
REF
V
V
V
V
R1
R2
SWITCH
FB
SWITCH
SWITCH
C
FB
(AC
V
O
,