CS51413EDR8G ON Semiconductor, CS51413EDR8G Datasheet - Page 8

• Manufacturer Part Number: CS51413EDR8G
• Description: IC REG BUCK LV 1.5A SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of CS51413EDR8G

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Current - Output: 1.5A
• Frequency - Switching: 520kHz
• Voltage - Input: 4.5 ~ 40 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Style: SMD/SMT
• Primary Input Voltage: 40V
• No. Of Outputs: 1
• Output Current: 1.5A
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Current Rating: 1.5A
• Filter Terminals: SMD
• Input Voltage Primary Max: 40V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: CS51413EDR8GOS

Control Ramp Generation
generated from the converter’s output ripple. Using a current
derived ramp provides the same benefits as current mode,
namely input feed forward, single pole output filter
compensation and fast feedback following output load
transients. Typically a tantalum or organic polymer
capacitor is selected having a sufficiently large ESR
component, relative to its capacitive and ESL ripple
contributions, to ensure the control ramp was sensing
inductor current and its amplitude was sufficient to maintain
loop stability. This technique is illustrated in Figure 6.
such that MLCC’s can provide a cost effective filter solution
for low voltage (< 12 V), high frequency converters
(>200 kHz). For example, a 10 mF MLCC 16 V in a
805 SMT package has an ESR of 2 mW and an ESL of
100 nH. Using several MLCC’s in parallel, connected to
power and ground planes on a PCB with multiple vias, can
provide a “near perfect” capacitor. Using this technique,
output switching ripple below 10 mV can be readily
obtained since parasitic ESR and ESL ripple contributions
are nil. In this case, the control ramp is generated elsewhere
in the circuit.
where the L/DCR time constant of the output inductor is
matched with the CR time constant of the integrating
network, is shown in Figure 7. The converter’s transient
response following a 1 A step load is shown in Figure 8. This
transient response is indicative of a closed loop in excess of
10 kHz having good gain and phase margin in the frequency
domain. Also note the amplitude of output switching ripple
provided by just two 10 mF MLCC’s.
In original V2 designs, the control ramp VCR was
Advances in multilayer ceramic capacitor technology are
Ramp generation using dcr inductor current sensing,
V
Figure 6. Control Ramp Generated from Output
IN
V
FB
L
C
C
esr
V
OUT
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8
is illustrated in Figure 9.
V
IN
Figure 9. Control Ramp from Voltage Feed Forward
Ramp generation using a voltage feed forward technique
V
IN
Figure 7. Control Ramp Generated from DCR
Inductor Sensing
V
V
FB
FB
R
Figure 8.
R
C
f
f
C
C
Z
V
V
OUT
OUT