KS8995XA Micrel Inc, KS8995XA Datasheet
KS8995XA
Specifications of KS8995XA
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KS8995XA Summary of contents
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... KS8995XA General Description The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for ...
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... Home networking expansion • Standalone 10/100 switch • Hotel/campus/MxU gateway • Enterprise VoIP gateway/phone • FTTx customer premise equipment • Media converter Ordering Information Part Number Temp. Range KS8995XA 0°C to +70°C 128-Pin PQFP KSZ8995XA 0°C to +70°C 128-Pin PQFP 2 Micrel, Inc. Package ...
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... KS8995XA Revision History Revision Date Summary of Changes 2.0 10/15/03 Created. 2.1 4/1/04 Editorial changes on TTL input and output electrical characteristics. 2.2 1/19/05 Insert recommeneded reset circuit. 2.3 4/13/05 Switched pins names for pins 7 & page 16. Changed VDDIO to 3.3V. Changed Jitter Max. ...
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... KS8995XA Table of Contents System Level Applications .............................................................................................................................................................. 6 Pin Description (by Number) ........................................................................................................................................................... 8 Pin Description (by Name) ............................................................................................................................................................ 13 Pin Configuration ........................................................................................................................................................................... 18 Introduction ............................................................................................................................................................................ 19 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19 100BASE-TX Transmit ............................................................................................................................................................ 19 100BASE-TX Receive ............................................................................................................................................................. 19 PLL Clock Synthesizer ............................................................................................................................................................ 19 Scrambler/De-scrambler (100BASE-TX only) ......................................................................................................................... 19 100BaseFX Operation ............................................................................................................................................................. 19 100BaseFX Signal Detection ................................................................................................................................................... 20 100BaseFX Far End Fault ....................................................................................................................................................... 20 10BASE-T Transmit ................................................................................................................................................................. 20 10BASE-T Receive ...
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... KS8995XA Register 8 (0x08): Global Control 6 ................................................................................................................................ 32 Register 9 (0x09): Global Control 7 ................................................................................................................................ 32 Register 10 (0x0A): Global Control 8 ............................................................................................................................. 32 Register 11 (0x0B): Global Control 9 ............................................................................................................................. 33 Port Registers .......................................................................................................................................................................... 33 Register 16 (0x10): Port 1 Control 0 .............................................................................................................................. 33 Register 17 (0x11): Port 1 Control 1 .............................................................................................................................. 34 Register 18 (0x12): Port 1 Control 2 .............................................................................................................................. 34 Register 19 (0x13): Port 1 Control 3 .............................................................................................................................. 35 Register 20 (0x14): Port 1 Control 4 ...
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... MAC 5 PHY 5 EEPROM Ethernet MAC MII-SW MII-P5 KS8995XA Ethernet MAC Exte rnal W Figure 1. Broadband Gateway MII-SW CPU KS8995XA Ethernet MAC Figure 2. Integrated Broadband Router 6 4-port LAN 1-port WAN I/F EEPROM I/F AN port PHY not required. 10/100 10/100 PHY 1 MAC 1 10/100 ...
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... KS8995XA May 2005 10/100 10/100 MAC 1 PHY 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 PHY 5 EEPROM I/F KS8995XA Figure 3. Standalone Switch 7 5-port LAN EEPROM M9999-051305 Micrel, Inc. ...
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... KS8995XA Pin Description (by Number) Pin Number Pin Name Type 1 MDI-XDIS 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXP2 14 TXM2 15 VDDAR 16 GNDA Gnd 17 ISET 18 VDDAT 19 RXP3 20 RXM3 21 GNDA Gnd 22 TXP3 23 TXM3 24 VDDAT 25 RXP4 26 RXM4 27 GNDA ...
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... KS8995XA Pin Number Pin Name Type 31 VDDAR 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd MUX1 MUX2 47 PWRDN_N 48 RESERVE/NC 49 GNDD Gnd 50 VDDC 51 PMTXEN 52 PMTXD3 53 PMTXD2 54 PMTXD1 55 PMTXD0 56 PMTXER 57 PMTXC 58 GNDD Gnd 59 VDDIO ...
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... KS8995XA Pin Number Pin Name Type 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD Gnd 77 VDDIO 78 SMRXC 79 SMRXDV Ipd/O 80 SMRXD3 Ipd/O 81 SMRXD2 Ipd/O 82 SMRXD1 Ipd/O 83 SMRXD0 Ipd/O 84 SCOL Ipd/O ...
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... KS8995XA Pin Number Pin Name Type 86 SCONF1 87 SCONF0 88 GNDD Gnd 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 Ipu/O 95 LED4-0 Ipu/O 96 LED3-2 Ipu/O 97 LED3-1 Ipu/O 98 LED3-0 Ipu/O 99 GNDD Gnd 100 VDDIO 101 LED2-2 Ipu/O 102 LED2-1 Ipu/O 103 LED2-0 ...
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... Output clock at 81kHz in I I/O All Serial data input/output in I All No connect Ipd No connect or pull-down. Ipd No connect or pull-down. Ipu Reset the KS8995XA. Active low. Digital ground. P 1.8V digital core V Ipd Factory test pin. Ipd Factory test pin connection. I 25MHz crystal clock connection/or 3.3V tolerant oscillator input. ...
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... KS8995XA Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 2 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 16 GNDA Gnd 21 GNDA Gnd 27 GNDA Gnd 30 GNDA Gnd 34 GNDA Gnd 40 GNDA Gnd 42 GNDA Gnd 44 GNDA Gnd 120 NC 124 GNDA Gnd 126 GNDA Gnd 127 ...
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... KS8995XA Pin Number Pin Name Type 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO Ipu MUX1 MUX2 68 PCOL Ipd/O 67 PCRS Ipd/O 60 PMRXC 65 PMRXD0 Ipd/O 64 PMRXD1 Ipd/O 63 PMRXD2 Ipd/O 62 PMRXD3 Ipd/O 61 PMRXDV ...
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... KS8995XA Pin Number Pin Name Type 47 PWRDN_N 48 RESERVE/NC 109 Reserved 112 Reserved 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 4 RXP1 10 RXP2 19 RXP3 25 RXP4 32 RXP5 119 SCANEN 110 SCL 84 SCOL Ipd/O 87 SCONF0 86 SCONF1 85 SCRS Ipd/O 111 SDA 78 SMRXC 83 SMRXD0 Ipd/O Notes Power supply. ...
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... KS8995XA Pin Number Pin Name Type 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER 1 MDIXDIS 128 TEST2 118 TESTEN 7 TXP1 13 TXP2 22 TXP3 28 TXP4 35 TXP5 8 TXM1 14 TXM2 23 TXM3 29 TXM4 36 TXM5 123 VDDAP 3 VDDAR 15 VDDAR 31 VDDAR ...
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... KS8995XA Pin Number Pin Name Type 9 VDDAT 18 VDDAT 24 VDDAT 37 VDDAT 50 VDDC 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note Power supply Input Output. May 2005 (1) Port Pin Function P 2.5V or 3.3V analog V P 2.5V or 3.3V analog V P 2.5V or 3.3V analog ...
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... KS8995XA Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 M9999-051305 128-Pin PQFP (PQ) 18 Micrel, Inc. 65 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC ...
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... The major enhancements from the KS8995E to the KS8995XA are support for programmable rate limiting, a dual MII interface, MDC/MDIO control interface for IEEE 802.3-defined register configuration (not all the registers), per-port broadcast storm protection, local loopback and lower power consumption ...
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... Power Management The KS8995XA features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shutdown. ...
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... The KS8995XA has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. ...
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... KS8995XA will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995XA will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times ...
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... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995XA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995XA has an MTXER pin, it should be tied low. ...
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... MRXER Receive data bit 3 MRXD3 Receive data bit 2 MRXD2 Receive data bit 1 MRXD1 Receive data bit 0 MRXD0 Receive clock MRXC Table 2. MII – SW Signals 24 Micrel, Inc. KS8995XA Signal SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] ...
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... Advanced Functionality QoS Support The KS8995XA is a QoS switch, meaning that is it able to identify selected packets on its ingress ports, prioritize them, and service the packets according to their priority on the egress ports. In this way, the KS8995XA can provide statistically better service to the high priority packets that are latency sensitive, or require higher bandwidth. The KS8995XA supports ingress QoS classification using three different mechanisms: port-based priority, 802 ...
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... If the DiffServ classification is enabled on a port, the KS8995XA will decode the IPv4 DiffServ field and look at the user defined code point bit to determine if the packet is high priority or low priority. If the code point is a ‘1’, the packet is high priority. If the code point is ‘ ...
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... The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995XA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. ...
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... Figure 10. EEPROM Configuration Timing Diagram To configure the KS8995XA with a pre-configured EEPROM use the following steps: • At the board level, connect pin 110 on the KS8995XA to the SCL pin on the EEPROM. Connect pin 111 on the KS8995XA to the SDA pin on the EEPROM. • Be sure the board-level reset signal is connected to the KS8995XA reset signal on pin 115 (RST_N). ...
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... KS8995XA Register Map Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port 2 Status Registers 48-61 0x30-0x3D ...
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... KS8995XA Address Name Register 2 (0x02): Global Control 0 (continued) 2 Buffer share mode 1 UNH mode 0 Link change age Register 3 (0x03): Global Control 1 7 Pass all frames 6 Reserved 5 IEEE 802.3x transmit flow control disable 4 IEEE 802.3x receive flow control disable 3 Frame length field check ...
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... KS8995XA Address Name Register 4 (0x04): Global Control 2 7 Reserved 6 Multicast storm protection disable 5 Reserved 4 Flow control and back pressure fair mode 3 No excessive collision drop 2 Huge packet support 1 Legal maximum packet size check disable 0 Priority buffer reserve Register 5 (0x05): Global Control 3 ...
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... KS8995XA Address Name Register 5 (0x05): Global Control 3 (continued) 1 Reserved 0 Sniff mode select Register 6 (0x06): Global Control 4 7 Switch MII back pressure enable 6 Switch MII half duplex mode 5 Switch MII flow control enable 4 Switch MII 10BT 3 Null VID replacement 2-0 Broadcast storm ...
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... KS8995XA Address Name Register 11 (0x0B): Global Control 9 7-4 Reserved 3 PHY power save 2 Factory setting 1 LED mode 0 Reserved Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. ...
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... KS8995XA Address Name 1 Tag removal 0 Priority enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 Address Name 7 Sniffer port 6 Receive sniff 5 Transmit sniff 4-0 Port VLAN membership Register 18 (0x12): Port 1 Control 2 ...
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... KS8995XA Address Name 3 Back pressure enable 2 Transmit enable 1 Receive enable 0 Learning disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address Name 7-0 Default tag [15:8] Register 20 (0x14): Port 1 Control 4 ...
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... KS8995XA Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): Port 5 Control 7 Address Name 7-4 Transmit low priority rate control [11:8] 3-0 Transmit high priority rate control [11:8] Register 24 (0x18): Port 1 Control 8 ...
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... KS8995XA Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 Address Name 7 Receive differential priority rate control 6 Low priority receive rate control enable 5 High priority receive rate control enable 4 Low priority receive rate ...
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... KS8995XA Address Name 5 Forced duplex 4 Advertised flow control capability 3 Advertised 100BT full-duplex capability 2 Advertised 100BT half-duplex capability 1 Advertised 10BT full-duplex capability 0 Advertised 10BT half-duplex capability Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 ...
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... KS8995XA Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 Address Name 7 MDIX status 6 AN done 5 Link good 4 Partner flow control capability 3 Partner 100BT full-duplex capability 2 Partner 100BT half-duplex capability 1 Partner 10BT full-duplex capability ...
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... KS8995XA Address Name Register 97 (0x61): TOS Priority Control Register 1 7-0 DSCP[55:48] Register 98 (0x62): TOS Priority Control Register 2 7-0 DSCP[47:40] Register 99 (0x63): TOS Priority Control Register 3 7-0 DSCP[39:32] Register 100 (0x64): TOS Priority Control Register 4 7-0 DSCP[31:24] Register 101 (0x65): TOS Priority Control Register 5 ...
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... KS8995XA Address Name 9 Restart AN 8 Force full-duplex 7 Collision test 6 Reserved 5 Reserved 4 Force MDI 3 Disable auto MDIX 2 Disable far end fault 1 Disable transmit 0 Disable LED Register 1: MII Status 15 T4 capable 14 100 Full capable 13 100 Half capable 12 10 Full capable 11 10 Half capable ...
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... KS8995XA Address Name 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Selector field Register 5: Link Partner Ability 15 Next page 14 LP ACK 13 Remote fault 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 full 7 Adv 100 half 6 Adv 10 full 5 Adv 10 half ...
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... KS8995XA Absolute Maximum Ratings Supply Voltage ( ............................. –0.5V to +2.4V DDAR, DDAP, DDC ( ........................................ –0.5V to +4.0V DDAT, DDIO Input Voltage (All Inputs) ............................. –0.5V to +4.0V Output Voltage (All Outputs) ....................... –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270°C Storage Temperature (T ) ....................... –55°C to +150°C S Electrical Characteristics ...
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... KS8995XA Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of I SET SET Output Jitters 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/Fall Times M9999-051305 ...
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... KS8995XA Timing Diagrams Receive Timing SCL SDA Figure 11. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 12. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 t Output Valid OV1 May 2005 ...
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... KS8995XA Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-051305 ts2 tcyc2 th2 Figure 13. SNI Input Timing tcyc2 tov2 Figure 14. SNI Output Timing Table 8. SNI Timing Parameters 46 Micrel, Inc ...
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... KS8995XA Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 15. MAC Mode MII Timing – Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 16. MAC Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) CYC3 t Clock Cycle (10BASE-T) ...
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... KS8995XA Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 17. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 18. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) CYC4 t Clock Cycle (10BASE-T) ...
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... KS8995XA Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC Reset Circuit Diagram Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8895XA device. For the application where the reset circuit signal comes from another device (e ...
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... KS8995XA Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max ...
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... KS8995XA Package Information MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...