SI8452AA-B-IS1 Silicon Laboratories Inc, SI8452AA-B-IS1 Datasheet - Page 20

• Manufacturer Part Number: SI8452AA-B-IS1
• Description: IC ISOLATOR 5CH 5.5V 16-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: ISOpror

Specifications of SI8452AA-B-IS1

• Number Of Channels: 5
• Package / Case: 16-SOIC (3.9mm Width)
• Inputs - Side 1/side 2: 3/2
• Isolation Rating: 1000Vrms
• Voltage - Supply: 2.7 V ~ 5.5 V
• Data Rate: 1Mbps
• Propagation Delay: 35ns
• Output Type: Tri-State
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: SMD/SMT
• Propagation Delay Time: 35 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si8450/51/52/55
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
20
Notes:
Input
X
X
X
X
V
1. VDDI and VDDO are the input and output power supplies. V
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is
4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to
5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
H
L
7
7
7
7
I
1,2
is the enable control input located on the same output side.
operating in noisy environments.
VDD, or tied to GND.
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 26 for more details.
Input
H or NC
H or NC
H or NC
EN
X
L
L
1,2,3,4
7
State
VDDI
UP
UP
P
P
P
P
1,5,6
Table 12. Si845x Logic Operation Table
State
VDDO
UP
P
P
P
P
P
1,5,6
Undetermined Upon transition of VDDO from unpowered to pow-
V
O
Hi-Z or L
Hi-Z or L
Output
Rev. 1.3
H
L
L
8
8
1,2
I
and V
Disabled.
ered, V
than 1 µs.
Disabled.
ered, V
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V
returns to Hi-Z within 1 µs if EN is L.
Enabled, normal operation.
Upon transition of VDDI from unpowered to pow-
O
are the respective input and output terminals. EN
O
O
returns to the same state as V
returns to the same state as V
Comments
I
I
in less
within
O