ACPL-M61L-000E Avago Technologies US Inc., ACPL-M61L-000E Datasheet - Page 9

OPTOCOUPLER 10MBD ULP 5-SOIC

ACPL-M61L-000E

Manufacturer Part Number
ACPL-M61L-000E
Description
OPTOCOUPLER 10MBD ULP 5-SOIC
Manufacturer
Avago Technologies US Inc.
Series
R²Coupler™r
Datasheet

Specifications of ACPL-M61L-000E

Package / Case
6-SOIC (0.173", 4.40mm Width) 5 Leads
Voltage - Isolation
3750Vrms
Number Of Channels
1, Unidirectional
Current - Output / Channel
10mA
Data Rate
10MBd
Propagation Delay High - Low @ If
46ns @ 6.5mA
Current - Dc Forward (if)
8mA
Input Type
DC
Output Type
Push-Pull, Totem-Pole
Mounting Type
Surface Mount
Isolation Voltage
3750 Vrms
Maximum Fall Time
12 ns
Maximum Rise Time
12 ns
Output Device
Logic Gate Photo IC
Configuration
1 Channel
Maximum Baud Rate
10 MBps
Maximum Forward Diode Voltage
6.5 V
Maximum Reverse Diode Voltage
5 V
Maximum Power Dissipation
20 mW
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
No. Of Channels
1
Optocoupler Output Type
Logic Gate
Input Current
150mA
Output Voltage
7V
Opto Case Style
SOIC
No. Of Pins
5
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-2169-5
ACPL-M61L-000E
Package Characteristics
All typicals are at T
^ Advanced information, subject to change.
Notes:
1. t
2. PWD is defined as |t
3. t
4. CM
5. CM
6. CM
9
Parameter
Input-Output Insulation
Input-Output Resistance
Input-Output Capacitance
t
signal.
recommended operating conditions.
than 10 ns.
PHL
PLH
PSK
H
L
D
is equal to the magnitude of the worst case difference in t
propagation delay is measured from the 50% (V
propagation delay is measured from the 50% (V
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
A
PHL
= 25°C.
- t
PLH
|.
Symbol
V
R
C
I-O
ISO
I-O
Part Number
ACPL-061L^
ACPL-064L
ACPL-M61L
ACPL-W61L
ACPL-K64L
in
in
or I
or I
F
) on the rising edge of the input pulse to the 50% V
F
) on the falling edge of the input pulse to the 50% level of the rising edge of the V
PHL
and/or t
Min
3750
5000
PLH
that will be seen between units at any given temperature within the
Typ
10
0.6
12
Max
Units
V
:
pF
rms
DD
of the falling edge of the V
Test Conditions
RH < 50% for 1 min.
T
V
f = 1 MHz, T
A
I-O
= 25°C
= 500 V
A
= 25°C
O
signal.
O

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