DS1972-F5+ Maxim Integrated Products, DS1972-F5+ Datasheet
DS1972-F5+
Specifications of DS1972-F5+
Related parts for DS1972-F5+
DS1972-F5+ Summary of contents
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... Probes ♦ Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed Onto its Rim ♦ Presence Detector Acknowledges When Reader First Applies Voltage PART 16.25mm DS1972-F5+ DS1972-F3+ 2D ® + Denotes a lead(Pb)-free/RoHS-compliant package. ® 17.35mm Features Common iButton Features ...
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EEPROM iButton ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND .......................................-0.5V to +6V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These ...
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... Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to t Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS1972 present. RSTL Minimum limit maximum limit is t PDHMAX Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards ...
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... Note: Numbers in bold are not in compliance with legacy 1-Wire product standards. 4 _______________________________________________________________________________________ PROG L increases. A increases. A LEGACY VALUES OVERDRIVE SPEED (μs) MAX MIN MAX (undefined) 7 (undefined) (undefined 240 8 24 120 6 16 DS1972 VALUES STANDARD SPEED OVERDRIVE SPEED (μs) (μs) MIN MAX MIN 65* (undefined) 8* (undefined) 480 640 240 8 60 120 6 MAX 15.5 ...
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... Data is transferred serially through the 1- Wire protocol, which requires only a single data contact and a ground return. The DS1972 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the register page ...
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... Figure 7. All data is read and written least significant bit first. 64-Bit Lasered ROM Each DS1972 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits ...
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... Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS1972 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into four memory pages (32 bytes each). These four pages are the primary data memory ...
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... Writing data to the scratchpad clears this flag. To write data to the DS1972, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad ...
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... Memory Function Commands The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the DS1972. An example on how to use these functions to write to and read from the device is in the Memory Function Example section. The communication between the master and the DS1972 takes place either at standard speed (default overdrive speed ( ...
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... THE BITWISE LOGICAL N BYTE COUNTER AND OF THE TRANSMITTED BYTE AND THE DATA BYTE FROM THE TARGETED ADDRESS INTO THE SCRATCHPAD. N BUS MASTER Rx CRC-16 OF COMMAND, ADDRESS, E/S BYTE, AND DATA BYTES AS SENT BY THE DS1972 N BUS MASTER MASTER Tx RESET? Rx "1"s AAh TO FIGURE E[2:0]? ...
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... SCRATCHPAD PROG DATA TO ADDRESS DS1972 Tx "0" BUS MASTER Rx "1"s Y MASTER Tx RESET? N DS1972 Tx "1" N MASTER Tx RESET 1-Wire IDLE HIGH FOR POWER. DS1972 SETS MEMORY ADDRESS = (T[15:0]) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y BUS MASTER MASTER Tx RESET? Rx "1" MASTER Tx RESET? Y ADDRESS < 8Fh? ...
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... E/S, and scratchpad contents are not affected by a Read Memory command. 1-Wire Bus System The 1-Wire bus is a system that has a single bus mas- ter and one or more slaves. In all instances the DS1972 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken 12 ...
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... The presence pulse lets the bus master know that the DS1972 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...
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... MATCH ROM SEARCH ROM COMMAND? COMMAND DS1972 Tx BIT 0 MASTER Tx BIT 0 DS1972 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS1972 Tx BIT 1 MASTER Tx BIT 1 DS1972 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS1972 Tx BIT 63 MASTER Tx BIT 63 DS1972 Tx BIT 63 MASTER Tx BIT BIT 63 MATCH? BIT 63 MATCH? ...
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TO FIGURE 9a FROM FIGURE 9a FROM FIGURE 9a TO FIGURE 9a NOTE: THE OD FLAG REMAINS THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED. Figure 9b. ROM Functions Flowchart (continued) ...
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... A t RSTL overdrive mode, returning the device to standard speed. If the DS1972 is in overdrive mode and t no longer than 80µs, the device remains in overdrive mode. If the device is in overdrive mode and t between 80µs and 480µs, the device resets, but the communication speed is undetermined ...
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... When responding with a 1, the DS1972 does not hold the data line low at all, and the voltage starts rising as soon as t The sum of t ...
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... W1L V PUP V IHMASTER ILMAX RESISTOR WRITE-ZERO TIME SLOT V PUP V IHMASTER ILMAX RESISTOR READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 11. Read/Write Timing Diagrams 18 ______________________________________________________________________________________ ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS1972 ...
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... In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC generator inside the DS1972 iButton (Figure 13) calculates a new 16-bit CRC, as shown in the command flowchart (Figure 7). The bus master compares the CRC value ...
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... Figure 13. CRC-16 Hardware Description and Polynomial by the bus master. The DS1972 transmits this CRC only if E[2:0] = 111b. With the Read Scratchpad command, the CRC is gen- erated by first clearing the CRC generator and then shifting in the command code, the target addresses Command-Specific 1-Wire Communication Protocol—Legend ...
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Command-Specific 1-Wire Communication Protocol—Color Codes Master to Slave Slave to Master Write Scratchpad (Cannot Fail) RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop Read Scratchpad (Cannot Fail) RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop Copy ...
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... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE F3 iButton F5 iButton 22 ______________________________________________________________________________________ With only a single DS1972 connected to the bus mas- ter, the communication looks like this: DATA (LSB FIRST) (Reset) Reset pulse (Presence) Presence pulse CCh Issue “ ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2010 Maxim Integrated Products ...