MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet
MT4VDDT3264HY-335F2
Specifications of MT4VDDT3264HY-335F2
MT4VDDT3264HY-335F2
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MT4VDDT3264HY-335F2 Summary of contents
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... SR) 200-PIN DDR SDRAM SODIMM MT4VDDT864H – 64MB MT4VDDT1664H – 128MB MT4VDDT3264H – 256MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) 1.25in. (31.75mm) OPTIONS • Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free) • ...
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... MT4VDDT3264HG-26A__ 256MB MT4VDDT3264HY-26A__ 256MB 256MB MT4VDDT3264HG-265__ MT4VDDT3264HY-265__ 256MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT4VDDT1664HG-265A1. pdf: 09005aef8086ea3d, source: 09005aef8086ea0b DD4C8_16_32x64HG.fm - Rev. C 9/04 EN 64MB, 128MB, 256MB (x64, SR) ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 118, 119, 120 WE#, CAS#, RAS# 35, 37, 158, 160 CK0, CK0#, CK1, CK1# 96 121 ...
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... V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DDR SDRAMs DDR SDRAMs CK1 DDR SDRAMs U1, U2 CK1# Standard modules use the following DDR SDRAM devices: MT46V8M16TG (64MB); MT46V16M16TG (128MB); MT46V32M16TG (256MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V8M16P (64MB); MT46V16M16P (128MB); MT46V32M16P (256MB) 6 CS# UDQS UDM DQ32 ...
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... DDR SDRAMs DDR SDRAMs CK1 DDR SDRAMs U1, U2 CK1# Standard modules use the following DDR SDRAM devices: MT46V8M16TG (64MB); MT46V16M16TG (128MB); MT46V32M16TG (256MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/ MT46V8M16P (64MB); MT46V16M16P (128MB); MT46V32M16P (256MB) 7 CS# UDQS UDM DQ ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... BA0 A11 A10 Operating Mode CAS Latency BT * M13 and M12 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 128MB and 256MB Modules BA1 BA0 A12 A11 A10 Operating Mode CAS Latency BT * M14 and M13 (BA1 and BA0) must be “ ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES LENGTH ADDRESS WITHIN A BURST TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 ...
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... DD4C8_16_32x64HG.fm - Rev. C 9/04 EN 64MB, 128MB, 256MB (x64, SR) 200-PIN DDR SDRAM SODIMM Figure 7: Extended Mode Register Definition Diagram The 64MB Module BA1 BA0 A11 A10 Operating Mode 128MB, 256MB Modules BA1 BA0 A12 A11 A10 Operating Mode E11 E10 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 64MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 13: I Specifications and Conditions – 128MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); ...
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Table 14: I Specifications and Conditions – 256MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 15: Capacitance Note: 11; notes appear on pages 19–22 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# (64MB) Input Capacitance: CK, CK# (128MB, 256MB) Table 16: DDR SDRAM Component Electrical ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12-15, 29; notes appear on pages 19–22; 0°C AC CHARACTERISTICS PARAMETER Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2), ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK/ inputs, collectively during device bank active. 31. READs and WRITEs with auto precharge are not t allowed to be ...
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Figure 11: Reduced Output Pull-Down Characteristics 0.0 0.5 1.0 V (V) OUT e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 14, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 28 BYTE DESCRIPTION 0 Number of SPD Bytes Used By Micron 1 Total Number of Bytes In SPD Device 2 Fundamental Memory Type ...
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... The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef8086ea3d, source: 09005aef8086ea0b DD4C8_16_32x64HG.fm - Rev. C 9/04 EN 64MB, 128MB, 256MB (x64, SR) 200-PIN DDR SDRAM SODIMM ENTRY (VERSION) ...
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Figure 18: 200-Pin SODIMM Dimensions –64MB 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.091 (2.30) 0.085 (2.15) U6 PIN 200 NOTE: All dimensions are in inches (millimeters;) pdf: 09005aef8086ea3d, source: 09005aef8086ea0b DD4C8_16_32x64HG.fm - Rev. C 9/04 EN ...
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Figure 19: 200-Pin SODIMM Dimensions – 128MB, 256MB 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): This ...