MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 11

MODULE DDR 256MB 200-SODIMM

MT4VDDT3264HY-335F2

Manufacturer Part Number
MT4VDDT3264HY-335F2
Description
MODULE DDR 256MB 200-SODIMM
Manufacturer
Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
780mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1231
MT4VDDT3264HY-335F2
Commands
Operation Truth Table, below, provide a general refer-
ence of available commands. For a more detailed
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select device bank and activate row)
READ (Select device bank and column, and start READ burst)
WRITE (Select device bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in device bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Figure 8, Commands Truth Table, and Figure 9, DM
DESELECT and NOP are functionally interchangeable.
BA0–BA1 provide device bank address and A0–A12 provide row address.
BA0–BA1 provide device bank address; A0–A8 (128MB) or A0–A9 (256MB), provide column address; A10 HIGH enables
the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
READ bursts with auto precharge enabled and for WRITE bursts.
A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-
BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
11
description of commands and operations, refer to the
256Mb or 512Mb DDR SDRAM component data sheet.
128MB, 256MB (x64, SR) PC3200
CS#
200-PIN DDR SDRAM SODIMM
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
H
H
H
H
X
L
L
L
L
CAS# WE#
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
DM
X
X
X
X
H
L
©2004 Micron Technology, Inc.
NOTES
Valid
DQS
6, 7
X
1
1
2
3
3
4
5
8

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