MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 18

• Manufacturer Part Number: MT4VDDT3264HY-335F2
• Description: MODULE DDR 256MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 780mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1231; MT4VDDT3264HY-335F2

pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge may be
32. Any positive glitch in the nominal voltage must be
33. Normal Output Drive Curves:
ing by the DRAM controller greater than eight
refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock has a maximum duty cycle variation of
45/55, beyond which functionality is uncertain.
result in a fail value. CKE is HIGH during RE-
FRESH command period (
LOW (i.e., during standby).
the input must:
be 1 V/ns (2 V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4 V/ns, functionality is uncer-
tain. For -40B, slew rates must be 0.5 V/ns.
not active while any device bank is active.
timing parameter may vary by the same amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during device bank active.
issued after
the internal precharge command is issued.
less than 1/3 of the clock and not more than
+300mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
cycle and not exceed either -200mV or 2.4V mini-
mum, whichever is more positive. The average
cannot be below the +2.6V minimum.
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
a. The full variation in driver pull-down current
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
t
QH =
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
from minimum to maximum process, temper-
ature and voltage will lie within the outer
must not vary more than 4 percent if CKE is
t
IH
IH
HP -
(AC).
(DC).
t
t
RAS(MIN) has been satisfied prior to
QHS). The data valid window derates
t
HP (
t
t
t
CK/2),
CL minimum and
RFC [MIN]) else CKE is
t
DQSQ, and
t
DS and
IL
IL
(DC)
(AC)
t
t
QH
CH
18
34. Reduced Output Drive Curves:
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
b. The variation in driver pull-down current
d. The variation in driver pull-up current within
b. The variation in driver pull-down current
d. The variation in driver pull-up current within
a. The full variation in driver pull-down current
c. The full variation in driver pull-up current
e. The full variation in the ratio of the maximum
c. The full variation in driver pull-up current
f. The full variation in the ratio of the nominal
Micron Technology, Inc., reserves the right to change products or specifications without notice.
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics, on page 19.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Pull-Down Characteristics,
on page 19.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics, on page 19.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 8, Pull-Up Characteristics, on page 19.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Reduced Output Pull-Down Characteristics,
on page 19.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Reduced Output Pull-Down
Characteristics, on page 19.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Reduced Output Pull-Up Characteristics, on
page 19.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 10, Reduced Output Pull-Up Character-
istics, on page 19.
©2004 Micron Technology, Inc.