MT18VDDF12872G-40BD3 Micron Technology Inc, MT18VDDF12872G-40BD3 Datasheet - Page 20

• Manufacturer Part Number: MT18VDDF12872G-40BD3
• Description: MODULE DDR SDRAM 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872G-40BD3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1114

pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
IH
IL
DD
RPST), or begins driving (
TT
(MIN) = -1.5V for a pulse width
overshoot: V
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
DQSCK (MIN) +
DD
DD
DD
level and the referenced test load. In
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
(MAX) = V
t
RPRE (MAX) condition.
t
RPRE begin point are not
DD
DD
t
Q, V
t
LZ (MIN) will prevail
RPRE).
+ 0.3V. Alternatively,
TT
t
DD
DQSCK (MAX) +
, and V
Q + 1.5V for a
IL
undershoot:
3ns and the
REF
must
TT
20
512MB, 1GB (x72, ECC, SR) PC3200
41. For -40B, I
42. Random address changing and 50 percent of data
43. Random address changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
SDRAM device at 100 MHz.
changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic high or logic low.
REF later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
2N specifies the DQ, DQS, and DM to be
2
F
is “worst case.”
DD
DD
DD
3
2
N
F
2
, I
is specified to be 35mA per DDR
F
DD
except I
2
N
, and I
©2004 Micron Technology, Inc. All rights reserved.
DD
DD
2Q specifies the
2Q are similar,
DD
2Q is