MT18VDDF12872G-335F1 Micron Technology Inc, MT18VDDF12872G-335F1 Datasheet - Page 23

• Manufacturer Part Number: MT18VDDF12872G-335F1
• Description: MODULE DDR SDRAM 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872G-335F1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
32. Any positive glitch must be less than 1/3 of the
33. Normal Output Drive Curves:
34. The voltage levels used are derived from a mini-
160
140
120
100
80
60
40
20
0
0.0
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
mum V
practice, the voltage levels obtained from a prop-
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 10.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 11.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 11.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
DD
Figure 10: Pull-Down
0.5
level and the referenced test load. In
1.0
V
V
OUT
OUT
(V)
(V)
1.5
2.0
Minimum
2.5
23
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -335, -262, -26A and -265, I
42. Random address changing and 50 percent of data
43. Random address changing and 100 percent of
44. CKE must be active (high) during the entire time a
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
be 35mA per DDR SDRAM at 100 MHz.
changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
REF later.
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
TT
184-PIN DDR SDRAM RDIMM
(MIN) = -1.5V for a pulse width
overshoot: V
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
512MB, 1GB (x72, ECC, SR)
DQSCK (MIN) +
DD
0.5
Figure 11: Pull-Up
DD
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
1.0
V
(MAX) = V
DD Q
t
RPRE (MAX) condition.
t
RPRE begin point are not
- V
DD
©2004 Micron Technology, Inc. All rights reserved.
OUT
DD
t
Q, V
t
LZ (MIN) will prevail
(V)
RPRE).
1.5
+ 0.3V. Alternatively,
DD
TT
t
DD
DQSCK (MAX) +
, and V
3
Q + 1.5V for a
N
IL
is specified to
undershoot:
3ns and the
2.0
REF
must
TT
2.5