Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 105
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
When the Timer Output alternate function TxOUT on a GPIO port pin is en-
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
0 = Timer counts when the Timer Input signal is High (1) and interrupts are
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are
0 = Counting is started on the first rising edge of the Timer Input signal. The
1 = Counting is started on the first falling edge of the Timer Input signal. The
The timer input clock is divided by 2
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
abled, TxOUT will change to whatever state the TPOL bit is in. The timer does
not need to be enabled for that to happen. Also, the Port data direction sub reg-
ister is not needed to be set to output on TxOUT. Changing the TPOL bit with
the timer enabled and running does not immediately change the TxOUT.
generated on the falling edge of the Timer Input.
current count is captured on subsequent rising edges of the Timer Input signal.
generated on the rising edge of the Timer Input.
current count is captured on subsequent falling edges of the Timer Input signal.
, where PRES can be set from 0 to 7. The
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