Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 122
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
The receiver generates an interrupt when any of the following occurs:
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and should be ignored. The
cates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data register must be read again to clear the
error bits is the UART Status 0 register. Updates to the Receive Data register occur only
when the next data word is received.
UART Data and Error Handling Procedure
interrupt service routines.
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
A break is received
An overrun is detected
A data framing error is detected
on page 109 displays the recommended procedure for use in UART receiver
Z8 Encore! XP
bit is set to 1 to indicate that