Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 143
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format PHASE Equals Zero
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
one. The diagram may be interpreted as either a Master or Slave timing diagram because
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
Transfer Format PHASE Equals One
one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for
CLKPOL set to 1.
displays the timing diagram for an SPI transfer in which PHASE is cleared to 0.
on page 130 displays the timing diagram for an SPI transfer in which PHASE is
Figure 24. SPI Timing When PHASE is 0
Z8 Encore! XP
Serial Peripheral Interface