Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 145



Manufacturer Part Number

Specifications of Z8F64220100ZDA

Module/board Type
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Error Detection
SPI Interrupts
register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUM-
BITS field in the SPIMODE register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL register may be used if desired to force a “startup”
interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register
are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE mode so
the SPIBRH and SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT
register is not written prior to the slave transaction, the MISO pin outputs whatever value
is currently in the SPIDAT register.
Due to the delay resulting from synchronization of the SPI input signals to the internal
system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is
the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
The SPI contains error detection logic to support SPI communication protocols and
recognize when communication errors have occurred. The SPI Status register indicates
when a data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data register was attempted
while a data transfer is in progress (in either MASTER or SLAVE modes). An overrun sets
the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error Flag. The
data register is not altered when a write occurs while data transfer is in progress.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to
COL clears this error Flag.
Slave Mode Abort
In SLAVE mode of operation if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The
next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous
transaction left off. Writing a 1 to ABT clears this error Flag.
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception completes in both MASTER and SLAVE modes. A character can be
Z8 Encore! XP
Product Specification
Serial Peripheral Interface
F64XX Series

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