Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 149
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 65. SPI Status Register (SPISTAT)
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
SPI Status Register
The SPI Status register
their reset state if the SPIEN bit in the SPICTL register = 0.
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
If SPI enabled as a Slave,
65) indicates the current state of the SPI. All bits revert to
Z8 Encore! XP
Serial Peripheral Interface