Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 158
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Address Only Transaction with a 7-bit Address
reading the I
next data byte.
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
with a 7-bit address will acknowledge. As an example, this transaction can be used after a
‘write’ has been done to a EEPROM to determine when the EEPROM completes its inter-
nal write operation and is once again responding to I
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
Follow the steps below for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
5. Software sets the START and STOP bits of the I
6. The I
7. The I
8. Software polls the STOP bit of the I
to the I
bit when the address only transaction is completed.
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the STOP bit was set.
Software checks the ACK bit of the I
Figure 27. 7-Bit Address Only Transaction Format
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
C Data register. As an alternative this could be a read operation instead of a
C Data register. Once the I
displays this ‘address only’ transaction to determine if a slave
C Shift register with the contents of the I
W = 0 A/A
C Control register. Hardware deasserts the STOP
C Control register.
C data register has been read, the I
C Control register to enable Transmit interrupts.
C Status register. If the slave acknowledged, the
C Data register is empty (TDRE = 1)
C Control register and clears the TXI
C transactions. If the slave does not
Z8 Encore! XP
C reads the