Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 167
Manufacturer Part Number
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Specifications of Z8F64220100ZDA
For Use With/related Products
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 70. I
Table 71. I
C Status Register
C Data Register (I2CDATA)
C Status Register (I2CSTAT)
The Read-only I
TDRE—Transmit Data Register Empty
When the I
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit is cleared by reading the I
cution of the On-Chip Debugger’s Read Register command).
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
C Controller is enabled, this bit is 1 when the I
C Status register
C Controller is enabled and the I
C Data register (unless the read is performed using exe-
71) indicates the status of the I
C Controller to generate an interrupt.
Z8 Encore! XP
C Data register is empty.
C Controller has received a