C8051T610DB24 Silicon Laboratories Inc, C8051T610DB24 Datasheet - Page 143

DAUGHTER BOARD T610 24QFN SOCKET

C8051T610DB24

Manufacturer Part Number
C8051T610DB24
Description
DAUGHTER BOARD T610 24QFN SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051T610DB24

Module/board Type
Socket Module - QFN
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1507
22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. As a receiver, the interrupt for an ACK occurs before the ACK. As a transmitter,
interrupts occur after the ACK.
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK
cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 22.5. Typical Master Write Sequence
W
A
Interrupt Locations
Data Byte
Rev 1.0
C8051T610/1/2/3/4/5/6/7
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
A
P
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