C8051T610DB24 Silicon Laboratories Inc, C8051T610DB24 Datasheet - Page 60

• Manufacturer Part Number: C8051T610DB24
• Description: DAUGHTER BOARD T610 24QFN SOCKET
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T610DB24

• Module/board Type: Socket Module - QFN
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610DK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1507

C8051T610/1/2/3/4/5/6/7
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN
(for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 12.1). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or nega-
tive hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the
setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “16.1. MCU Interrupt Sources and Vectors” on page 86). The
CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Compar-
ator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
60
(Programmed with CPnHYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CPn-
VIN+
CPn+
VIN-
Disabled
V
OL
Figure 12.3. Comparator Hysteresis Plot
V
OH
+
_
CPn
Positive Hysteresis
Maximum
OUT
Rev 1.0
Negative Hysteresis
Disabled
Negative Hysteresis
(Programmed by CPnHYN Bits)
Maximum
Negative Hysteresis Voltage