C8051T600SDB Silicon Laboratories Inc, C8051T600SDB Datasheet

BOARD SOCKET DAUGHTER SOIC

C8051T600SDB

Manufacturer Part Number
C8051T600SDB
Description
BOARD SOCKET DAUGHTER SOIC
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051T600SDB

Module/board Type
Socket Module - SOIC
Data Bus Width
8 bit
Operating Supply Voltage
+ 1.8 V to + 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051T600DK
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1405
Rev. 1.2 3/09
Analog Peripherals
-
-
On-Chip Debug
-
-
-
Supply Voltage 1.8 to 3.6 V
-
-
Temperature Range: –40 to +85 °C
Package Options:
-
-
-
-
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
10-Bit ADC (‘T600/602/604 only)
Comparator
C8051F300 can be used as code development 
platform; complete development kit available
On-chip debug circuitry facilitates full speed, 
non-intrusive in-system debug
Provides breakpoints, single stepping, 
inspect/modify memory and registers
On-chip LDO for internal core supply
Built-in voltage supply monitor
3 x 3 mm QFN11
2 x 2 mm QFN10 (C8051T606 Only)
MSOP10 (C8051T606 Only)
SOIC14 (C8051T600/1/2/3/4/5 Only)
Up to 500 ksps
Up to 8 external inputs
V
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
REF
external pin, Internal Regulator or V
INTERRUPTS
M
A
U
X
C8051T600/2/4
1.5/2/4/8kB
EPROM
PERIPHERALS
CALIBRATED PRECISION INTERNAL
500ksps
HIGH-SPEED CONTROLLER CORE
12
ANALOG
Copyright © 2009 by Silicon Laboratories
10-bit
ADC
DD
COMPARATOR
VOLTAGE
OSCILLATOR
Mixed-Signal Byte-Programmable EPROM MCU
SENSOR
+
-
CIRCUITRY
TEMP
8051 CPU
(25MIPS)
DEBUG
High-Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
Clock Sources
-
-
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
256 or 128 Bytes internal data RAM
8, 4, 2, or 1.5 kB byte-programmable EPROM code
memory
Up to 8 Port I/O with high sink current capability
Hardware enhanced UART and SMBus™ serial
ports
Three general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with three
capture/compare modules
Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
External oscillator: RC, C, or CMOS Clock
Can switch between clock sources on-the-fly; useful
in power saving modes
C8051T600/1/2/3/4/5/6
DIGITAL I/O
Timer 0
Timer 1
Timer 2
SMBus
UART
8 or 16-bit PWM
Rising / falling edge capture
Frequency output
Software timer
PCA
POR
128/256 B
SRAM
WDT
C8051T600/1/2/3/4/5/6

C8051T600SDB Summary of contents

Page 1

Analog Peripherals - 10-Bit ADC (‘T600/602/604 only 500 ksps • external inputs • V external pin, Internal Regulator or V • REF Internal or external start of conversion source • Built-in temperature sensor • - ...

Page 2

C8051T600/1/2/3/4/5/6 Table of Contents 1. System Overview ..................................................................................................... 13 2. Ordering Information ............................................................................................... 16 3. Pin Definitions.......................................................................................................... 17 4. QFN-11 Package Specifications ............................................................................. 22 5. SOIC-14 Package Specifications ............................................................................ 24 6. MSOP-10 Package Specifications .......................................................................... 26 7. QFN-10 Package Specifications ...

Page 3

Interrupt Register Descriptions ........................................................................ 82 17.3. INT0 and INT1 External Interrupt Sources ...................................................... 87 18. Power Management Modes................................................................................... 89 18.1. Idle Mode......................................................................................................... 89 18.2. Stop Mode ....................................................................................................... 90 19. Reset Sources ........................................................................................................ 92 19.1. Power-On Reset .............................................................................................. 93 19.2. ...

Page 4

C8051T600/1/2/3/4/5/6 23.3.2. Arbitration.............................................................................................. 122 23.3.3. Clock Low Extension............................................................................. 122 23.3.4. SCL Low Timeout.................................................................................. 122 23.3.5. SCL High (SMBus Free) Timeout ......................................................... 123 23.4. Using the SMBus........................................................................................... 123 23.4.1. SMBus Configuration Register.............................................................. 123 23.4.2. SMB0CN Control Register .................................................................... 127 23.4.3. Data ...

Page 5

C2 Pin Sharing .............................................................................................. 185 Document Change List.............................................................................................. 186 Contact Information................................................................................................... 188 C8051T600/1/2/3/4/5/6 Rev. 1.2 5 ...

Page 6

C8051T600/1/2/3/4/5/6 List of Figures 1. System Overview Figure 1.1. C8051T600/2/4 Block Diagram ............................................................. 14 Figure 1.2. C8051T601/3/5 Block Diagram ............................................................. 14 Figure 1.3. C8051T606 Block Diagram ................................................................... 15 2. Ordering Information 3. Pin Definitions Figure 3.1. C8051T600/1/2/3/4/5-GM QFN11 Pinout Diagram ...

Page 7

Comparator0 Figure 13.1. Comparator0 Functional Block Diagram ............................................. 59 Figure 13.2. Comparator Hysteresis Plot ................................................................ 60 Figure 13.3. Comparator Input Multiplexer Block Diagram ...................................... 63 14. CIP-51 Microcontroller Figure 14.1. CIP-51 Block Diagram ......................................................................... 65 15. Memory Organization Figure ...

Page 8

C8051T600/1/2/3/4/5/6 Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 156 26. Programmable Counter Array Figure 26.1. PCA Block Diagram ........................................................................... 160 Figure 26.2. PCA Counter/Timer Block Diagram ................................................... 161 Figure 26.3. PCA Interrupt Block Diagram ............................................................ 162 Figure 26.4. ...

Page 9

List of Tables 1. System Overview 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 16 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T600/1/2/3/4/5 ........................................... 17 Table 3.2. Pin Definitions for the C8051T606 .......................................................... 18 4. QFN-11 Package ...

Page 10

C8051T600/1/2/3/4/5/6 18. Power Management Modes 19. Reset Sources 20. EPROM Memory Table 20.1. Security Byte Decoding ........................................................................ 98 21. Oscillators and Clock Selection 22. Port Input/Output Table 22.1. Port I/O Assignment for Analog Functions ......................................... 109 Table 22.2. Port I/O ...

Page 11

List of Registers SFR Definition 9.1. ADC0CF: ADC0 Configuration ...................................................... 44 SFR Definition 9.2. ADC0H: ADC0 Data Word MSB .................................................... 45 SFR Definition 9.3. ADC0L: ADC0 Data Word LSB ...................................................... 45 SFR Definition 9.4. ADC0CN: ADC0 Control ................................................................ 46 SFR ...

Page 12

C8051T600/1/2/3/4/5/6 SFR Definition 25.1. CKCON: Clock Control .............................................................. 146 SFR Definition 25.2. TCON: Timer Control ................................................................. 151 SFR Definition 25.3. TMOD: Timer Mode ................................................................... 152 SFR Definition 25.4. TL0: Timer 0 Low Byte ............................................................... 153 SFR Definition 25.5. TL1: Timer ...

Page 13

System Overview C8051T600/1/2/3/4/5/6 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering num- bers. High-speed pipelined 8051-compatible microcontroller core ( MIPS)  ...

Page 14

C8051T600/1/2/3/4/5/6 CIP-51 8051 Controller Core 2k/4k/8k Byte Power On EPROM Program Reset Memory Reset Debug / C2CK/RST 256 byte SRAM Programming Hardware SYSCLK C2D Power Net VDD External GND EXTCLK Clock Circuit System Clock Configuration Figure 1.1. C8051T600/2/4 Block Diagram ...

Page 15

CIP-51 8051 Controller Core 1.5 k Byte EPROM Power On Program Memory Reset Reset C2CK/RST Debug / 128 Byte SRAM Programming Hardware SYSCLK C2D Power Net VDD External GND EXTCLK Clock Circuit System Clock Configuration Figure 1.3. C8051T606 Block Diagram ...

Page 16

C8051T600/1/2/3/4/5/6 2. Ordering Information Table 2.1. Product Selection Guide 1 C8051T600- C8051T600- C8051T601- C8051T601- C8051T602- C8051T602- C8051T603- C8051T603- C8051T604- ...

Page 17

Pin Definitions Table 3.1. Pin Definitions for the C8051T600/1/2/3/4/5 Name QFN11 SOIC14 Type Pin Pin GND 11 3 RST / I/O C2CK D I ...

Page 18

C8051T600/1/2/3/4/5/6 Table 3.2. Pin Definitions for the C8051T606 Name QFN11 MSOP10 QFN10 Pin Pin Pin GND GND* 11 — — RST / C2CK P0 C2D ...

Page 19

P0.0 / VREF P0.3 / EXTCLK 5 Figure 3.1. C8051T600/1/2/3/4/5-GM QFN11 Pinout Diagram (Top View) P0.6 / CNVSTR 1 P0.7 / C2D 2 GND P0.0 / ...

Page 20

C8051T600/1/2/3/4 P0.3 / EXTCLK 5 Figure 3.3. C8051T606-GM QFN11 Pinout Diagram (Top View P0 P0 P0.3 / EXTCLK ...

Page 21

P0 TOP VIEW P0 P0.3 / EXTCLK 4 Figure 3.5. C8051T606-ZM QFN10 Pinout Diagram (Top View) C8051T600/1/2/3/4/5/6 NC P0.7 / C2D 9 10 GND 8 RST / C2CK 7 5 P0.5 6 ...

Page 22

C8051T600/1/2/3/4/5/6 4. QFN-11 Package Specifications Figure 4.1. QFN-11 Package Drawing Table 4.1. QFN-11 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 3.00 BSC D2 1.30 1.35 e 0.50 BSC Notes: ...

Page 23

Figure 4.2. QFN-11 PCB Land Pattern Table 4.2. QFN-11 PCB Land Pattern Dimensions Dimension Min Max C1 2.75 2.85 C2 2.75 2.85 E 0.50 BSC X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise ...

Page 24

C8051T600/1/2/3/4/5/6 5. SOIC-14 Package Specifications Figure 5.1. SOIC-14 Package Drawing Table 5.1. SOIC-14 Package Dimensions Dimension Min Nom A — — A1 0.10 — b 0.33 — c 0.17 — D 8.65 BSC E 6.00 BSC E1 3.90 BSC e ...

Page 25

Figure 5.2. SOIC-14 Recommended PCB Land Pattern Table 5.2. SOIC-14 PCB Land Pattern Dimensions Dimension Min Max C1 5.30 5.40 E 1.27 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern ...

Page 26

C8051T600/1/2/3/4/5/6 6. MSOP-10 Package Specifications Figure 6.1. MSOP-10 Package Drawing Table 6.1. MSOP-10 Package Dimensions Dimension Min Nom A — — A1 0.00 — A2 0.75 0.85 b 0.17 — c 0.08 — D 3.00 BSC E 4.90 BSC E1 ...

Page 27

Figure 6.2. MSOP-10 PCB Land Pattern Table 6.2. MSOP-10 PCB Land Pattern Dimensions Dimension Min Max C1 4.40 REF E 0.50 BSC G1 3.00 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...

Page 28

C8051T600/1/2/3/4/5/6 7. QFN-10 Package Specifications Figure 7.1. QFN-10 Package Drawing Table 7.1. QFN-10 Package Dimensions Dimension Min Nom A 0.70 0.75 A1 0.00 — b 0.18 0.25 D 2.00 BSC. e 0.50 BSC. E 2.00 BSC. Notes: 1. All dimensions ...

Page 29

Figure 7.2. QFN-10 PCB Land Pattern Table 7.2. QFN-10 PCB Land Pattern Dimensions Dimension Min Max e 0.50 BSC. C1 1.70 1.80 C2 1.70 1.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...

Page 30

C8051T600/1/2/3/4/5/6 8. Electrical Characteristics 8.1. Absolute Maximum Specifications Table 8.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on RST or any Port I/O pin (except V during programming) with PP respect to GND Voltage on V ...

Page 31

Electrical Characteristics Table 8.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (Note 1) C8051T600/1/2/3/4/5 Digital Sup- ply Current with CPU Active C8051T600/1/2/3/4/5 Digital Sup- ply Current with CPU Inactive ...

Page 32

C8051T600/1/2/3/4/5/6 Table 8.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Tsysl (SYSCLK low time) Tsysh (SYSCLK high time) Notes: 1. Analog performance is not guaranteed when V 2. SYSCLK must be at ...

Page 33

Table 8.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull ...

Page 34

C8051T600/1/2/3/4/5/6 Table 8.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR ...

Page 35

Table 8.7. Internal High-Frequency Oscillator Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Oscillator Frequency IFCN = 11b Oscillator Supply Current  25 °C, V ...

Page 36

C8051T600/1/2/3/4/5/6 Table 8.10. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic ...

Page 37

Table 8.11. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: CP0+ – CP0– = 100 mV Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV Response Time: ...

Page 38

C8051T600/1/2/3/4/5/6 8.3. Typical Performance Curves 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 8.1. C8051T600/1/2/3/4/5 Normal Mode Supply Current vs. Frequency 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 8.2. C8051T606 Normal Mode Supply Current vs. ...

Page 39

Figure 8.3. C8051T600/1/2/3/4/5 Idle Mode Supply Current vs. Frequency 2.0 1.5 1.0 0.5 0 Figure 8.4. C8051T606 Idle Mode Digital Current vs. Frequency (MPCE = 1) C8051T600/1/2/3/4/5/6 V > 1.8 V ...

Page 40

C8051T600/1/2/3/4/5/6 9. 10-Bit ADC (ADC0, C8051T600/2/4 only) ADC0 on the C8051T600/2 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window detector. The ADC is fully configurable ...

Page 41

Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data ...

Page 42

C8051T600/1/2/3/4/5/6 9.3.2. Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left ...

Page 43

Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, ...

Page 44

C8051T600/1/2/3/4/5/6 SFR Definition 9.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the ...

Page 45

SFR Definition 9.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 ...

Page 46

C8051T600/1/2/3/4/5/6 SFR Definition 9.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. ...

Page 47

Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

Page 48

C8051T600/1/2/3/4/5/6 SFR Definition 9.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 9.8. ADC0LTL: ADC0 Less-Than Data Low ...

Page 49

Window Detector Example Figure 9.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned ...

Page 50

C8051T600/1/2/3/4/5/6 9.5. ADC0 Analog Multiplexer (C8051T600/2/4 only) ADC0 on the C8051T600/2/4 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 0 I/O pins, the ...

Page 51

SFR Definition 9.9. AMX0SL: AMUX0 Positive Channel Select Bit 7 6 Name R/W R/W Type 1 0 Reset SFR Address = 0xBB Bit Name 7:4 Unused Unused. Read = 1000b; Write = Don’t Care. 3:0 AMX0P[3:0] AMUX0 Positive Input Selection. ...

Page 52

C8051T600/1/2/3/4/5/6 10. Temperature Sensor (C8051T600/2/4 only) An on-chip temperature sensor is included on the C8051T600/2/4, which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured ...

Page 53

Figure 10.2. Temperature Sensor Error with 1-Point Calibration at 0 °C C8051T600/1/2/3/4/5/6 20.00 40.00 Temperature (degrees C) Rev. 1.2 5.00 4.00 3.00 2.00 1.00 0.00 60.00 ...

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C8051T600/1/2/3/4/5/6 SFR Definition 10.1. TOFFH: Temperature Offset Measurement High Byte Bit 7 6 Name Type Varies Varies Reset SFR Address = 0xA3 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Order Bits. The temperature sensor offset registers represent the output ...

Page 55

Voltage Reference Options The voltage reference multiplexer for the ADC is configurable for use with an externally connected voltage reference, the unregulated power supply voltage (V Figure 11.1). The REFSL bit in the Reference Control register (REF0CN, SFR Definition ...

Page 56

C8051T600/1/2/3/4/5/6 SFR Definition 11.1. REF0CN: Reference Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4 REGOVR Regulator Reference Override. This bit ...

Page 57

Voltage Regulator (REG0) C8051T600/1/2/3/4/5/6 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD ...

Page 58

C8051T600/1/2/3/4/5/6 SFR Definition 12.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xC7 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device ...

Page 59

Comparator0 C8051T600/1/2/3/4/5/6 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 13.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...

Page 60

C8051T600/1/2/3/4/5/6 externally driven from –0. trical specifications are given in Section “8. Electrical Characteristics” on page 30. The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 13.2). Selecting a ...

Page 61

Note that false rising edges and falling edges can be detected when the comparator is first powered changes are made to the hysteresis or response time control bits. Therefore recommended that the rising-edge and falling-edge ...

Page 62

C8051T600/1/2/3/4/5/6 SFR Definition 13.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:2 Unused Unused. Read = 000000b, Write = Don’t Care. 1:0 CP0MD[1:0] Comparator0 Mode Select. These ...

Page 63

Comparator Multiplexer C8051T600/1/2/3/4/5/6 devices include an analog input multiplexer to connect Port I/O pins to the compar- ator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 13.3). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; ...

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C8051T600/1/2/3/4/5/6 SFR Definition 13.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9F Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5:4 CMX0N[1:0] Comparator0 Negative Input MUX ...

Page 65

CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

Page 66

C8051T600/1/2/3/4/5/6 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion ...

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Table 14.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...

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C8051T600/1/2/3/4/5/6 Table 14.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A ...

Page 69

Table 14.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement ...

Page 70

C8051T600/1/2/3/4/5/6 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first ...

Page 71

CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to ...

Page 72

C8051T600/1/2/3/4/5/6 SFR Definition 14.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer ...

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SFR Definition 14.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted ...

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C8051T600/1/2/3/4/5/6 15. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...

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Data Memory The C8051T600/1/2/3/4/5 devices include 256 bytes of RAM, and the C8051T606 devices include 128 bytes of RAM. This memory is mapped into the internal data memory space of the 8051 controller core. The RAM memory organization of ...

Page 76

C8051T600/1/2/3/4/5/6 15.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of ...

Page 77

Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T600/1/2/3/4/5/6's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...

Page 78

C8051T600/1/2/3/4/5/6 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xC3 ADC0 Greater-Than Compare Low ADC0GTL 0xBE ADC0 High ADC0H 0xBD ADC0 Low ADC0L 0xC6 ADC0 Less-Than Compare Word ...

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Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xFA PCA Counter High PCA0H 0xF9 PCA Counter Low PCA0L 0xD9 PCA Mode PCA0MD 0x87 Power Control PCON 0xD0 Program ...

Page 80

C8051T600/1/2/3/4/5/6 17. Interrupts The C8051T600/1/2/3/4/5/6 includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal input pins varies according to the specific version ...

Page 81

MCU Interrupt Sources and Vectors The C8051T600/1/2/3/4/5/6 MCUs support 12 interrupt sources. Software can simulate an interrupt by set- ting an interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated ...

Page 82

C8051T600/1/2/3/4/5/6 Table 17.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SMB0 0x0033 ADC0 0x003B Window ...

Page 83

SFR Definition 17.1. IE: Interrupt Enable Bit IEGF0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. ...

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C8051T600/1/2/3/4/5/6 SFR Definition 17.2. IP: Interrupt Priority Bit 7 6 Name R R Type 1 1 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7:6 Unused Unused. Read = 11b, Write = Don't Care. 5 PT2 Timer 2 Interrupt Priority ...

Page 85

SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ECP0R Name R R Type 0 0 Reset SFR Address = 0xE6 Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5 ECP0R Enable Comparator0 (CP0) ...

Page 86

C8051T600/1/2/3/4/5/6 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PCP0R Name R R Type 1 1 Reset SFR Address = 0xF6 Bit Name 7:6 Unused Unused. Read = 11b; Write = Don’t Care. 5 PCP0R Comparator0 (CP0) ...

Page 87

INT0 and INT1 External Interrupt Sources The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...

Page 88

C8051T600/1/2/3/4/5/6 SFR Definition 17.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. ...

Page 89

Power Management Modes The C8051T600/1/2/3/4/5/6 devices have two software programmable power management modes: idle and stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted, all interrupts and timers ...

Page 90

C8051T600/1/2/3/4/5/6 18.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital ...

Page 91

SFR Definition 18.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop Mode ...

Page 92

C8051T600/1/2/3/4/5/6 19. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  CIP-51 halts program execution  Special Function Registers (SFRs) are initialized to ...

Page 93

Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...

Page 94

C8051T600/1/2/3/4/5/6 19.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 19.2). When level above V , ...

Page 95

EPROM Error Reset If an EPROM read or write targets an illegal address, a system reset is generated. This may occur due to any of the following:  Programming hardware attempts to write or read an EPROM location which ...

Page 96

C8051T600/1/2/3/4/5/6 SFR Definition 19.1. RSTSRC: Reset Source Bit 7 6 MEMERR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable ...

Page 97

EPROM Memory Electrically programmable read-only memory (EPROM) is included on-chip for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special pro- gramming voltage is applied to the V (i.e., ...

Page 98

C8051T600/1/2/3/4/5/6 20.1.2. EPROM Read Procedure 1. Reset the device using the RST pin. 2. Wait at least 20 µs before sending the first C2 command. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Write ...

Page 99

Program Memory CRC A CRC engine is included on-chip, which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and ...

Page 100

C8051T600/1/2/3/4/5/6 21. Oscillators and Clock Selection C8051T600/1/2/3/4/5/6 devices include a programmable internal high-frequency oscillator and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 21.1. ...

Page 101

Programmable Internal High-Frequency (H-F) Oscillator All C8051T600/1/2/3/4/5/6 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR ...

Page 102

C8051T600/1/2/3/4/5/6 SFR Definition 21.2. OSCICN: Internal H-F Oscillator Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xB2 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care 4 IFRDY Internal H-F Oscillator ...

Page 103

External Oscillator Drive Circuit The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also pro- vide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be wired ...

Page 104

C8051T600/1/2/3/4/5/6 SFR Definition 21.3. OSCXCN: External Oscillator Control Bit 7 6 XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 Unused Read = 0b; Write = Don’t Care 6:4 XOSCMD[2:0] External Oscillator Mode Select. 00x: ...

Page 105

External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than 100 pF; however ...

Page 106

C8051T600/1/2/3/4/5/6 22. Port Input/Output Digital and analog resources are available through eight I/O pins on the C8051T600/1/2/3/4/5, or six I/O pins on the C8051T606. Port pins P0.0-P0.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal ...

Page 107

Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the P0MDIN registers. On reset, all Port ...

Page 108

C8051T600/1/2/3/4/5/6 22.1.3. Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5. external pullup resistor ...

Page 109

Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins ...

Page 110

C8051T600/1/2/3/4/5/6 22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital ...

Page 111

Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 22.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...

Page 112

C8051T600/1/2/3/4/5/6 Port P0 Pin Special Function Signals TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings XBR0 ...

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Port P0 Pin Special Function Signals TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings XBR0 Figure ...

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C8051T600/1/2/3/4/5/6 22.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (P0MDIN). 2. Select the output mode (open-drain or push-pull) ...

Page 115

SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name R Type 0 0* Reset SFR Address = 0xE1 Bit Name 7 Unused Unused. Read = 0; Write = Don’t Care. 6:0 XSKP[6:0] Crossbar Skip Enable Bits. ...

Page 116

C8051T600/1/2/3/4/5/6 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 PCA0ME[1:0] Name R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7:6 PCA0ME[1:0] PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at ...

Page 117

SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE3 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for ...

Page 118

C8051T600/1/2/3/4/5/6 22.5. Special Function Registers for Accessing and Configuring Port I/O The Port I/O pins are accessed through the special function register P0, which is both byte addressable and bit addressable. When writing to this SFR, the value written is ...

Page 119

SFR Definition 22.5. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak pullup, ...

Page 120

C8051T600/1/2/3/4/5/6 23. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with ...

Page 121

Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, ...

Page 122

C8051T600/1/2/3/4/5/6 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE ...

Page 123

When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and ...

Page 124

C8051T600/1/2/3/4/5/6 Table 23.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as ...

Page 125

SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 23.2 shows the min- imum setup and hold times for ...

Page 126

C8051T600/1/2/3/4/5/6 SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...

Page 127

SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 23.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...

Page 128

C8051T600/1/2/3/4/5/6 SFR Definition 23.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is ...

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Table 23.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When:  A START is generated. MASTER  START is generated.  SMB0DAT is written before the start of an TXMODE SMBus frame.  A START followed by ...

Page 130

C8051T600/1/2/3/4/5/6 23.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...

Page 131

SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...

Page 132

C8051T600/1/2/3/4/5/6 23.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus ...

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Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte and a receiver during all data bytes. When slave events ...

Page 134

C8051T600/1/2/3/4/5/6 23.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave ...

Page 135

Table 23.4. SMBus Status Decoding Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte ...

Page 136

C8051T600/1/2/3/4/5/6 Table 23.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A slave byte was transmitted ...

Page 137

UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “24.1. ...

Page 138

C8051T600/1/2/3/4/5/6 24.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...

Page 139

Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 24.3. Figure 24.3. UART Interconnect Diagram 24.2.1. 8-Bit UART ...

Page 140

C8051T600/1/2/3/4/5/6 24.2.2. 9-Bit UART The 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a program- mable ninth data bit, and a stop bit. The state of the ninth ...

Page 141

Multiprocessor Communications The 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, ...

Page 142

C8051T600/1/2/3/4/5/6 SFR Definition 24.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: ...

Page 143

SFR Definition 24.2. SBUF0: Serial (UART0) Port Data Buffer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x99 Bit Name 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register ...

Page 144

C8051T600/1/2/3/4/5/6 Table 24.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: ...

Page 145

Timers Each MCU includes three counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...

Page 146

C8051T600/1/2/3/4/5/6 SFR Definition 25.1. CKCON: Clock Control Bit 7 6 T2MH Name R R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 Unused Unused. Read = 0b, Write = Don’t Care 6 T2MH Timer 2 High Byte ...

Page 147

Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to ...

Page 148

C8051T600/1/2/3/4/5/6 Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR INT0 Figure 25.1. T0 Mode 0 Block Diagram 25.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. ...

Page 149

Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...

Page 150

C8051T600/1/2/3/4/5/6 25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits ...

Page 151

SFR Definition 25.2. TCON: Timer Control Bit 7 6 TF1 TR1 Name R/W R/W Type 0 0 Reset SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Set hardware when Timer 1 overflows. ...

Page 152

C8051T600/1/2/3/4/5/6 SFR Definition 25.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective ...

Page 153

SFR Definition 25.4. TL0: Timer 0 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. ...

Page 154

C8051T600/1/2/3/4/5/6 SFR Definition 25.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer ...

Page 155

Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...

Page 156

C8051T600/1/2/3/4/5/6 25.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; ...

Page 157

SFR Definition 25.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the ...

Page 158

C8051T600/1/2/3/4/5/6 SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the ...

Page 159

SFR Definition 25.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the ...

Page 160

C8051T600/1/2/3/4/5/6 26. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit Capture/Compare modules. Each Capture/Compare module ...

Page 161

PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H ...

Page 162

C8051T600/1/2/3/4/5/6 26.2. PCA0 Interrupt Sources Figure 26.3 shows a diagram of the PCA interrupt tree. There are four independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which ...

Page 163

Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. Each module has Special Function Registers ...

Page 164

C8051T600/1/2/3/4/5/6 26.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit Capture/Compare register (PCA0CPLn and PCA0CPHn). ...

Page 165

Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit Capture/Com- pare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. ...

Page 166

C8051T600/1/2/3/4/5/6 26.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit Capture/Compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare ...

Page 167

Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The Capture/Compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the ...

Page 168

C8051T600/1/2/3/4/5/6 26.3.5. 8-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn Cap- ture/Compare register. When the value in the low byte of the PCA counter/timer (PCA0L) ...

Page 169

Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit Capture/Compare module defines the number of PCA clocks for the low time of the PWM signal. When the ...

Page 170

C8051T600/1/2/3/4/5/6 26.4. Watchdog Timer Mode A programmable Watchdog Timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified ...

Page 171

The 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset 256 PCA clocks may pass before the first PCA0L ...

Page 172

C8051T600/1/2/3/4/5/6 Table 26.3. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 3,062,500 3,062,500 3,062,500 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source and a PCA0L value of 0x00 at the update time. 2. Internal ...

Page 173

Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 26.1. PCA0CN: PCA Control Bit Name R/W R/W Type 0 0 Reset SFR ...

Page 174

C8051T600/1/2/3/4/5/6 SFR Definition 26.2. PCA0MD: PCA Mode Bit 7 6 CIDL WDTE WDLCK Name R/W R/W Type 0 1 Reset SFR Address = 0xD9 Bit Name 7 CIDL PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle ...

Page 175

SFR Definition 26.3. PCA0CPMn: PCA Capture/Compare Mode Bit 7 6 PWM16n ECOMn CAPPn Name R/W R/W Type 0 0 Reset SFR Addresses: PCA0CPM0 = 0xDA Bit Name 7 PWM16n 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when ...

Page 176

C8051T600/1/2/3/4/5/6 SFR Definition 26.4. PCA0L: PCA Counter/Timer Low Byte Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xF9 Bit Name 7:0 PCA0[7:0] PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of ...

Page 177

SFR Definition 26.6. PCA0CPLn: PCA Capture Module Low Byte Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Addresses: PCA0CPL0 = 0xFB Bit Name 7:0 PCA0CPn[7:0] PCA Capture Module Low Byte. The PCA0CPLn register holds the low byte ...

Page 178

C8051T600/1/2/3/4/5/6 27. C2 Interface C8051T600/1/2/3/4/5/6 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow EPROM programming and in-system debugging with the production part installed in the end application. The C2 interface operates using only two pins: a ...

Page 179

C2 Register Definition 27.2. DEVICEID: C2 Device ID Bit 7 6 Name Type 0 0 Reset C2 Address: 0x00 Bit Name 7:0 DEVICEID[7:0] Device ID. This read-only register returns the 8-bit device ID: 0x10 = C8051T600/1/2/3/4/5 0x1B = C8051T606 C2 ...

Page 180

C8051T600/1/2/3/4/5/6 C2 Register Definition 27.4. DEVCTL: C2 Device Control Bit 7 6 Name Type 0 0 Reset C2 Address: 0x02 Bit Name 7:0 DEVCTL[7:0] Device Control Register. This register is used to halt the device for EPROM operations via the ...

Page 181

C2 Register Definition 27.6. EPDAT: C2 EPROM Data Bit 7 6 Name Type 0 0 Reset C2 Address: 0xBF Bit Name 7:0 EPDAT[7:0] C2 EPROM Data Register. This register is used to pass EPROM data during C2 EPROM operations. C2 ...

Page 182

C8051T600/1/2/3/4/5/6 C2 Register Definition 27.8. EPADDRH: C2 EPROM Address High Byte Bit 7 6 Name Type 0 0 Reset C2 Address: 0xAF Bit Name 7:0 EPADDR[15:8] C2 EPROM Address High Byte. This register is used to set the EPROM address ...

Page 183

C2 Register Definition 27.10. CRC0: CRC Byte 0 Bit 7 6 Name Type 0 0 Reset C2 Address: 0xA9 Bit Name 7:0 CRC[7:0] CRC Byte 0. A write to this register initiates a 16-bit CRC of one 256-byte block of ...

Page 184

C8051T600/1/2/3/4/5/6 C2 Register Definition 27.12. CRC2: CRC Byte 2 Bit 7 6 Name Type 0 0 Reset C2 Address: 0xAB Bit Name 7:0 CRC[23:16] CRC Byte 2. See Section “20.3. Program Memory CRC” on page 99. C2 Register Definition 27.13. ...

Page 185

C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and EPROM programming functions may be performed. This is possible because C2 communication is typi- cally performed when the ...

Page 186

C8051T600/1/2/3/4/5 OCUMENT HANGE IST Revision 0.5 to Revision 1.0  Updated electrical specification tables based on test, characterization, and qualification data.  Updated with new formatting standards.  Corrected minor typographical errors throughout document.  Updated wording ...

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N : OTES C8051T600/1/2/3/4/5/6 Rev. 1.2 187 ...

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... Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 188 web page  ...

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