C8051T600SDB Silicon Laboratories Inc, C8051T600SDB Datasheet - Page 89

• Manufacturer Part Number: C8051T600SDB
• Description: BOARD SOCKET DAUGHTER SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T600SDB

• Module/board Type: Socket Module - SOIC
• Data Bus Width: 8 bit
• Operating Supply Voltage: + 1.8 V to + 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600DK
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1405

18. Power Management Modes
The C8051T600/1/2/3/4/5/6 devices have two software programmable power management modes: idle
and stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU
is halted, all interrupts and timers (except the missing clock detector) are inactive, and the internal oscilla-
tor is stopped (analog peripherals remain in their selected states; the external oscillator is not affected).
Since clocks are running in idle mode, power consumption is dependent upon the system clock frequency
and the number of peripherals left in active mode before entering idle. Stop mode consumes the least
power because the majority of the device is shut down with no clocks active. SFR Definition 18.1 describes
the Power Control Register (PCON) used to control the C8051T600/1/2/3/4/5/6's stop and idle power man-
agement modes.
Although the C8051T600/1/2/3/4/5/6 has idle and stop modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use.
18.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from idle mode when
a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction
that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
If enabled, the watchdog timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “19.6. PCA Watchdog Timer
Reset” on page 94 for more information on the use and configuration of the WDT.
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
Rev. 1.2
C8051T600/1/2/3/4/5/6
89