C8051T600SDB Silicon Laboratories Inc, C8051T600SDB Datasheet - Page 96

• Manufacturer Part Number: C8051T600SDB
• Description: BOARD SOCKET DAUGHTER SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T600SDB

• Module/board Type: Socket Module - SOIC
• Data Bus Width: 8 bit
• Operating Supply Voltage: + 1.8 V to + 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600DK
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1405

C8051T600/1/2/3/4/5/6
SFR Definition 19.1. RSTSRC: Reset Source
SFR Address = 0xEF
96
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
MEMERR EPROM Error Reset Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
C0RSEF Comparator0 Reset Enable
SWRSF
PINRSF
Unused
PORSF
Name
R
7
0
Unused.
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On/V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
MEMERR
Varies
R
6
Description
DD
C0RSEF
Monitor
Varies
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev. 1.2
4
Don’t care.
N/A
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Writing a 1 forces a sys-
tem reset.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a 1 enables the
V
ures it as a reset source.
Writing 1 to this bit while
the V
abled may cause a sys-
tem reset.
N/A
DD
monitor and config-
DD
WDTRSF
monitor is dis-
Varies
Write
R
3
MCDRSF
Varies
R/W
2
0
Set to 1 if EPROM
read/write error caused
the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 any time a power-
on or V
occurs.
When set to 1, all other
RSTSRC flags are inde-
terminate.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0