C8051T606ZDB Silicon Laboratories Inc, C8051T606ZDB Datasheet - Page 73
C8051T606ZDB
Manufacturer Part Number
C8051T606ZDB
Description
CARD DAUGHTER QFN10 SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheets
1.C8051T600EDB.pdf
(188 pages)
2.C8051T606TDB.pdf
(1 pages)
3.C8051T606TDB.pdf
(14 pages)
Specifications of C8051T606ZDB
Module/board Type
Socket Module - QFN
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T606
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1668
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SFR Definition 14.6. PSW: Program Status Word
SFR Address = 0xD0; Bit-Addressable
Name
Reset
Bit
4:3
Type
7
6
5
2
1
0
Bit
PARITY
RS[1:0]
Name
CY
AC
OV
F0
F1
R/W
CY
7
0
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
Overflow Flag.
This bit is set to 1 under the following circumstances:
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
R/W
AC
6
0
R/W
F0
5
0
Rev. 1.2
4
0
RS[1:0]
R/W
Function
C8051T600/1/2/3/4/5/6
3
0
R/W
OV
2
0
R/W
F1
1
0
PARITY
R
0
0
73
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