C8051T600QDB Silicon Laboratories Inc, C8051T600QDB Datasheet - Page 114

• Manufacturer Part Number: C8051T600QDB
• Description: BOARD SOCKET DAUGHTER QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T600QDB

• Module/board Type: Socket Module - QFN
• Data Bus Width: 8 bit
• Operating Supply Voltage: + 1.8 V to + 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600DK
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1406

C8051T600/1/2/3/4/5/6
22.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (P0MDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(P0MDOUT).
3. Select any pins to be skipped by the I/O crossbar using the XBR0 register.
4. Assign Port pins to desired peripherals.
5. Enable the crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as analog inputs. When a pin is configured as an analog input, its weak
pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the
analog input. Pins configured as digital inputs may still be used by analog peripherals; however this prac-
tice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by
setting the associated bits in XBR0). Port input mode is set in the P0MDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition
22.5 for the P0MDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode register
(P0MDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
P0MDOUT settings. When the WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR1 and XBR2 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR2 to 1 enables the crossbar. Until the crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table. An alternative is to use the Configuration Wizard utility available on the Silicon Laboratories web site
to determine the Port I/O pin-assignments based on the XBRn Register settings.
The crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are
disabled while the crossbar is disabled.
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