C8051T600QDB Silicon Laboratories Inc, C8051T600QDB Datasheet - Page 118

• Manufacturer Part Number: C8051T600QDB
• Description: BOARD SOCKET DAUGHTER QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T600QDB

• Module/board Type: Socket Module - QFN
• Data Bus Width: 8 bit
• Operating Supply Voltage: + 1.8 V to + 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600DK
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1406

C8051T600/1/2/3/4/5/6
22.5. Special Function Registers for Accessing and Configuring Port I/O
The Port I/O pins are accessed through the special function register P0, which is both byte addressable
and bit addressable. When writing to this SFR, the value written is latched to maintain the output data
value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the Port register can
always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write
instructions that target the Port 0 Latch register as the destination. The read-modify-write instructions
include ANL, ORL, XRL, JBC, CPL, INC, DEC, or DJNZ for any usage. However, when the destination is
an individual bit in P0, the read-modify-write instructions include MOV, CLR, or SETB. For all read-modify-
write instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR.
The XBR0 register allows the individual Port pins to be assigned to digital functions or skipped by the
crossbar. All Port pins used for analog functions, GPIO, or dedicated digital functions should have their
XBR0 bit set to 1.
The Port input mode of the I/O pins is defined using the Port 0 Input Mode register (P0MDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers and is not automatic.
The output driver characteristics of the I/O pins are defined using the Port 0 Output Mode register
(P0MDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
P0MDOUT settings.
SFR Definition 22.4. P0: Port 0
SFR Address = 0x80; Bit-Addressable
118
Name
Reset
7:0
Bit
Type
Bit
P0[7:0]
Name
7
1
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Note: Bits 6 and 0 on the C8051T606 are read-only.
6
1
Description
5
1
Rev. 1.2
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
1
P0[7:0]
R/W
Write
3
1
2
1
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
1
1
Read
0
1