C8051T600QDB Silicon Laboratories Inc, C8051T600QDB Datasheet - Page 94

• Manufacturer Part Number: C8051T600QDB
• Description: BOARD SOCKET DAUGHTER QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T600QDB

• Module/board Type: Socket Module - QFN
• Data Bus Width: 8 bit
• Operating Supply Voltage: + 1.8 V to + 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600DK
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1406

C8051T600/1/2/3/4/5/6
19.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 19.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is disabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
ate a system reset. The V
in RSTSRC to 1.
See Figure 19.2 for V
monitor reset. See Table 8.4 for complete electrical characteristics of the V
19.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 8.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
19.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the time specified in Section “8. Electrical Characteristics” on
page 30, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
19.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
19.6. PCA Watchdog Timer Reset
The watchdog timer (WDT) function of the programmable counter array (PCA) can be used to prevent soft-
ware from running out of control during a system malfunction. The PCA WDT function can be enabled or
disabled by software as described in Section “26.4. Watchdog Timer Mode” on page 170; the WDT is
enabled and clocked by SYSCLK/12 following any reset. If a system malfunction prevents user software
from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The state of the
RST pin is unaffected by this reset.
94
DD
monitor will still be enabled after the reset.
RST
, the CIP-51 will be released from the reset state. Note that even though internal data
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monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it has the potential to gener-
monitor is enabled and selected as a reset source by writing the PORSF flag
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Monitor
monitor is enabled by code and a software reset is performed, the
Rev. 1.2
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to drop below V
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monitor.
RST
, the power supply
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dropped below
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returns
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