C8051T630DB20 Silicon Laboratories Inc, C8051T630DB20 Datasheet

BOARD SOCKET DAUGHTER 20-QFN

C8051T630DB20

Manufacturer Part Number
C8051T630DB20
Description
BOARD SOCKET DAUGHTER 20-QFN
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051T630DB20

Module/board Type
Socket Module - QFN
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1465
Analog Peripherals
-
-
-
-
-
-
10-bit DAC (Current Mode)
Comparator
-
-
-
Memory
-
-
On-Chip Debug
-
-
Supply Voltage 1.8 to 3.6 V
-
-
Temperature Range: –40 to +85 °C
Development Kit: C8051T630DK
Small Form Factor
C2CK/RST
10-Bit ADC
Up to 500 ksps
Up to 16 external single-ended inputs
VREF from external pin, VDD, or internal regulator
Built-in temperature sensor
External conversion start input
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (< 0.5 µA)
768 bytes data RAM
8 kB EPROM OTP code memory (byte programmable)
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
C8051F336 can be used as in-system code development platform; com-
plete development kit available
On-chip LDO regulator for core supply
On-chip voltage supply monitor
GND
VDD
Peripheral Power
Programming
C2D
Power On
Hardware
Regulator
Debug /
EXTCLK
Reset
25 MIPS, 8 kB EPROM, 10-Bit ADC, 10-Bit DAC, Mixed-Signal MCU
Reset
Core Power
Low-Freq.
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
Controller Core
External
System Clock
Program Memory
Circuit
Configuration
8k Byte EPROM
CIP-51 8051
256 Byte SRAM
512 Byte XRAM
Copyright © 2008 by Silicon Laboratories
SYSCLK
SFR
Bus
High-Speed 8051 µC Core
-
-
-
Digital Peripherals
-
-
-
-
-
-
-
-
-
-
Package
-
-
VDD
Clock Sources
Timers 0,
Reference
‘T630/2/4 Only
SMBus
Voltage
10-bit
500ksps
ADC
UART
1, 2, 3
Analog Peripherals
PCA/
WDT
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
17 port I/O; All 5 V tolerant with high sink current
Hardware enhanced UART, SPI™, and SMBus™ serial ports
Four general purpose 16-bit counter/timers
Timer with Real-time clock capability
16-Bit programmable counter array (PCA) with five capture/compare
modules
Software timer
Two internal oscillators:
External oscillator: RC, C, or Clock
Can switch between clock sources on-the-fly
20-pin QFN
Pin Compatibile with C8051F33x Family of Devices
Digital Peripherals
SPI
Port I/O Configuration
CP0, CP0A
-
-
-
-
-
-
Crossbar Control
24.5 MHz with ±2% accuracy supports crystal-less UART operation
Low-power suspend mode with fast wake time
80 kHz low frequency, low-power
PWM
Rising/falling edge capture
Frequency output
VREF
VREF
Comparator
M
A
U
X
+
Crossbar
-
Decoder
10-bit
IDAC
Priority
Sensor
Temp
VDD
IDA0
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
C8051T630
P0.0/VREF
P0.1/IDA0
P0.2/VPP
P0.3/EXTCLK
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0/C2D
1.21.2008

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