C8051T610DB28 Silicon Laboratories Inc, C8051T610DB28 Datasheet - Page 101

• Manufacturer Part Number: C8051T610DB28
• Description: DAUGHTER BOARD T610 28QFN SOCKET
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T610DB28

• Module/board Type: Socket Module - QFN
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610DK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1506

19.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on or V
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
is enabled following a power-on reset.
Logic HIGH
RST
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
ramp time is defined as how fast V
RST
Figure 19.2. Power-On and V
monitor event timing. The maximum V
V
RST
DD
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
Power-On
PORDelay
Reset
T
) is typically less than 0.3 ms.
PORDelay
Rev 1.0
DD
DD
DD
C8051T610/1/2/3/4/5/6/7
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
RST
Monitor
Reset
VDD
level. For ramp times less than
RST
). Figure 19.2. plots the
DD
settles above
DD
VDD
DD
ramp time
monitor
101
t