C8051T610DB28 Silicon Laboratories Inc, C8051T610DB28 Datasheet - Page 160

• Manufacturer Part Number: C8051T610DB28
• Description: DAUGHTER BOARD T610 28QFN SOCKET
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T610DB28

• Module/board Type: Socket Module - QFN
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610DK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1506

C8051T610/1/2/3/4/5/6/7
24.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
160
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection
Master
Device
Master
Device
GPIO
MISO
MOSI
MISO
MOSI
SCK
SCK
NSS
Diagram
Diagram
Rev 1.0
MISO
MOSI
SCK
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
Device
Device
Device
Slave
Slave
Slave