ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 256
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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22. IRCOM - IR Communication Module
22.1
22.2
8077H–AVR–12/09
Features
Overview
•
•
•
•
•
XMEGA contains an Infrared Communication Module (IRCOM) IrDA 1.4 compatible module for
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-
abled. There is one IRCOM available, and this can be connected to any USART to enable
infrared pulse coding/decoding for that USART.
Figure 22-1. IRCOM connection to USARTs and associated port pins
The IRCOM is automatically enabled when a USART is set in IRCOM mode. When this is done
signals between the USART and the RX/TX pins are routed through the module as shown in
ure 22-1 on page
input for the IRCOM receiver. This will disable the RX input from the USART pin.
Pulse modulation/demodulation for infrared communication
IrDA 1.4 Compatible for baud rates up to 115.2 kbps
Selectable pulse modulation scheme
Built in filtering
Can be connected to and used by any USART
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
IRCOM
Decoding
Encoding
Pulse
Pulse
256. It is also possible to select an Event Channel from the Event System as
encoded RXD
decoded TXD
decoded RXD
encoded TXD
Event System
USARTxn
....
DIF
USARTD0
USARTC0
events
RXDnx
TXDnx
XMEGA A
RXD...
TXD...
RXDD0
TXDD0
RXDC0
TXDC0
Fig-
256
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