ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 26
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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4.15.4
4.15.5
4.15.6
4.15.7
8077H–AVR–12/09
DATA2 - Non-Volatile Memory Data Register Byte 2
DATA1 - Non-Volatile Memory Data Register 1
DATA0 - Non-Volatile Memory Data Register 0
CMD - Non-Volatile Memory Command Register
The DATA2, DATA1 and ADDR0 registers represents the 24-bit value DATA.
• Bit 7:0 - DATA[23:16]: NVM Data Register 2
This register gives the data value byte 2 when running CRC check on application section, boot
section or combined.
• Bit 7:0 - DATA[15:8]: NVM Data Register Byte 1
This register gives the data value byte 1 when accessing application and boot section.
• Bit 7:0 - DATA[7:0]: NVM Data Register Byte 0
This register gives the data value byte 0 when accessing either of the memory locations.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:0 -CMD[6:0]: NVM Command
These bits define the programming commands for the flash. Bit six is set for external program-
ming commands. See "Memory Programming data sheet" for programming commands.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
R/W
R/W
R/W
R
7
0
7
0
7
0
7
0
-
R/W
R/W
R/W
R
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
DATA[23:16]
DATA[15:8]
DATA[7:0]
CMD[6:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DATA2
DATA1
DATA0
CMD
26
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