ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 272
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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24.6.5
24.6.6
24.7
24.7.1
8077H–AVR–12/09
SRAM LPC Configuration
Address Latch Requirements
Timing
Multiplexing Data with Address Byte 0
Figure 24-5. Multiplexed SRAM connection using ALE1 and ALE2
The Address Latch timing and parameter requirements are described in
277.
SRAM or external memory devices may have different timing requirements. To meet these vary-
ing requirements, each Chip Select can be configured with different wait-states. Timing details is
described in
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing
modes where the data and address lines are multiplexed. Compared to SRAM configuration,
this can further reduce the number of pins required for the EBI. The available configurations is
shown in
Timing and Address Latch requirements is as for SRAM configuration.
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same
port, and the ALE1 signal from the device controls the address latch.
Figure 24-6. Multiplexed SRAM LPC connection using ALE1
Section 24.7.1 on page 272
”EBI Timing” on page
EBI
EBI
A[23:16]/
A[19:16]
A[15:8]/
AD[7:0]
A[15:8]
D[7:0]
A[7:0]
ALE1
ALE2
ALE1
277.
through
D
G
Q
Section 24.7.2 on page
D
G
D
G
Q
Q
D[7:0]
A[7:0]
A[15:8]
A[23:16]
D[7:0]
A[7:0]
A[15:8]
A[19:16]
273.
SRAM
SRAM
”EBI Timing” on page
XMEGA A
272
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