ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 304
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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25.16.4
8077H–AVR–12/09
EVCTRL - ADC Event Control Register
Table 25-3.
Notes:
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – BANDGAP: Bandgap enable
Setting this bit enables the bandgap to prepare for ADC measurement. Note that if any other
functions are using the bandgap already, this bit does not need to be set. This could be when the
internal 1.00V reference is used in ADC or DAC, or if the Brown-out Detector is enabled.
• Bit 0 – TEMPREF: Temperature Reference enable
Setting this bit enables the temperature reference to prepare for ADC measurement.
• Bits 7:6 - SWEEP[1:0]: ADC Channel Sweep
These bits control which ADC channels are included in a channel sweep triggered by the event
system or in free running mode. See
Table 25-4.
• Bits 5:3 - EVSEL[2:0]: event channel input select
These bits define which event channel should trigger which ADC channel. Each setting defines a
group of event channels, where the event channels with the lowest number will trigger ADC
channel 0 and the next event channel will trigger ADC channel 1 and so on. The number of
incoming event in use is defined by the EVACT bits. See
Bit
+0x03
Read/Write
Initial Value
REFSEL[1:0]
SWEEP[1:0]
1. Only available if AREF exist on PORT A.
2. Only available it AREF exist on PORT B.
10
11
00
01
10
11
00
01
(1)
(2)
R/W
7
0
ADC Reference Configuration
ADC Channel Select
SWEEP[1:0]
R/W
6
0
Group Configuration
Group Configuration
INTVCC
AREFB
AREFA
INT1V
0123
R/W
012
5
0
01
0
Table 25-4 on page
EVSEL[2:0]
R/W
4
0
Description
Internal 1.00V
Internal V
External reference from AREF pin on PORT A.
External reference from AREF pin on PORT B.
Active ADC channels for channel sweep
Only ADC channel 0
ADC channels 0 and 1
ADC channels 0, 1, and 2
ADC channels 0, 1, 2, and 3
R/W
3
0
CC
Table 25-5 on page
304.
/1.6
R/W
2
0
EVACT[2:0]
R/W
1
0
XMEGA A
305.
R/W
0
0
EVCTRL
304
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