ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 325
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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26.10.7.1
26.10.7.2
26.10.8
26.10.8.1
26.10.8.2
26.10.9
8077H–AVR–12/09
CH0DATAL – DAC Channel 0 Data Register Low
CH1DATAH – DAC Channel 1 Data Register High
Right-adjusted
Left-adjusted
Right-adjusted
Left-adjusted
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:0 - CHDATA[11:8]: DAC Conversion Data Register Channel 0, 4 MSB
These bits are the 4 MSB of the 12-bit value to convert to channel 0 in right-adjusted mode.
• Bits 7:0 - CHDATA[11:4]: DAC Conversion Data Register Channel 0, 8 MSB
These bits are the 8 MSB of the 12-bit value to convert to channel 0 in left-adjusted mode.
• Bits 7:0 - CHDATA[7:0]: DAC Conversion Data Register Channel 0, 8 LSB
These bits are the 8 LSB of the 12-bit value to convert to channel 0 in right-adjusted mode.
• Bits 7:4 - CHDATA[3:0]: DAC Conversion Data Register Channel 0, 4 LSB
These bits are the 4 LSB of the 12-bit value to convert to channel 0 in left-adjusted mode.
• Bits 3:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Bit
+0x18
Read/Write
Read/Write
Initial Value
Initial Value
Bit
+0x1B
Read/Write
Read/Write
Initial Value
Initial Value
7
R/W
R/W
R/W
R
0
0
7
0
0
-
6
R/W
R/W
R/W
R
0
0
6
0
0
-
CHDATA[3:0]
5
R/W
R/W
R/W
R
0
0
5
0
0
-
4
R/W
R/W
R/W
0
0
4
R
0
0
CHDATA[11:4]
-
CHDATA[7:0]
3
R/W
R/W
R/W
R
0
0
3
0
0
-
2
R/W
R/W
R/W
R
0
0
2
0
0
-
CHDATA[11:8]
XMEGA A
1
R/W
R/W
R/W
R
0
0
1
0
0
-
0
R/W
R/W
R/W
R
0
0
0
0
0
-
325
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