ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 338
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATAVRDISPLAYX
Manufacturer:
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28.3
8077H–AVR–12/09
TAP - Test Access Port
When using the JTAG interface for Boundary-scan, the JTAG TCK clock frequency can be
higher than the internal device frequency. The System Clock in the device is not required for
Boundary-scan.
The JTAG interface is accessed through four of the AVR's pins. In JTAG terminology, these pins
constitute the Test Access Port - TAP. These pins are:
The IEEE std. 1149.1-2001 also specifies an optional TAP signal; TRST - Test ReSeT. This is
not available.
When the JTAGEN Fuse is unprogrammed or the JTAG Disable bit is set the JTAG interface is
disabled. The four TAP pins are normal port pins and the TAP controller is in reset. When
enabled, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-
scan operations.
Figure 28-1. TAP Controller state diagram
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
machine.
(Scan Chains).
XMEGA A
338
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