OM6290 NXP Semiconductors, OM6290 Datasheet
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PCF8531 34 x 128 pixel matrix driver Rev. 05 — 10 August 2010 1. General description The PCF8531 is a low-power CMOS matrix graphic displays at multiplex rates of 1:17, 1:26, and 1:34. Furthermore, it can drive up to 128 ...
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... NXP Semiconductors Icon mode Low-power consumption, suitable for battery operated systems CMOS compatible inputs Manufactured in silicon gate CMOS process 3. Applications Telecommunication systems Automotive information systems Point-of-sale terminals Instrumentation 4. Ordering information Table 1. Ordering information Type number Package Name PCF8531U - PCF8531 Product data sheet ...
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... NXP Semiconductors 5. Block diagram V LCDSENSE Fig 1. PCF8531 Product data sheet R0 to R33 34 V ROW SS1 DRIVERS V SS2 T1 T2 PCF8531 T3 T4 BIAS V VOLTAGE LCDIN GENERATOR V LCD GENERATOR V LCDOUT SCL INPUT SDA FILTERS CONTROL SDACK Block diagram of PCF8531 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF8531 Product data sheet R32 C31 C32 . . . . . . C63 C64 . . . . . . C95 C96 . . . . . . C127 R33 . . . . . . R1 pad1 The positioning of the bonding pads is not to scale. Bonding pad location for PCF8531 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 2. Pad center Fig 3. Table 3. Alignment marks circle 1 circle 2 PCF8531 Product data sheet Pad allocation table Symbol OSC V LCDSENSE V LCDOUT V LCDIN RES V DD3 V DD2 V DD1 SDA SDACK SA0 100 y μm center x center circle Alignment markers Alignment markers for PCF8531 All information provided in this document is subject to legal disclaimers. Rev. 05 — ...
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... NXP Semiconductors Fig 4. Table 4. Pad pad pitch (minimum) bump dimensions wafer thickness (excluding bumps) die size L × W 6.2 Pin description Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol - - - - - ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol V LCDOUT V LCDOUT V LCDOUT V LCDOUT V LCDOUT V LCDOUT V LCDOUT V LCDIN V LCDIN V LCDIN V LCDIN V LCDIN V LCDIN V LCDIN RES V DD3 V DD3 V DD3 V DD2 V DD2 ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol T4 V SS2 V SS2 V SS2 V SS2 V SS2 V SS2 V SS2 V SS1 V SS1 V SS1 V SS1 V SS1 V SS1 V SS1 T3 T1 SCL SCL - - - R10 PCF8531 ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R32 C10 C11 C12 C13 C14 C15 C16 C17 C18 ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 ...
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... NXP Semiconductors Table 5. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 ...
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... NXP Semiconductors [1] If the on-chip oscillator is used, this input must be connected to V [2] If the internal V [ external V will be damaged. [4] If only the internal Power-On Reset (POR) is used, this input must be connected to V [5] V DD1 V DD3 connected together. [6] Serial data acknowledge for the I fully I advantageous in Chip-On-Glass (COG) applications ...
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... NXP Semiconductors 7. Functional description 7.1 Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to V signal, if used, is connected to this input. 7.2 Power-On Reset (POR) The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure. ...
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... NXP Semiconductors 7.10 Bias voltage generator The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges: • Normal mode: 4 9.0 V • ...
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... NXP Semiconductors 8. LCD waveforms and DDRAM to data mapping The LCD waveforms and the DDRAM to display data mapping are shown in Figure 6 V LCD ROW 0 R0( LCD ROW 1 R1( LCD COL 0 C0( LCD COL 1 C1( LCD − − LCD state1 − LCD − ...
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... NXP Semiconductors V LCD ROW LCD ROW LCD COL 1 on/off LCD COL 2 off/ LCD COL 3 on/ LCD COL 4 off/off Fig 6. LCD waveforms, icon mode, multiplex rate 1:2 PCF8531 Product data sheet frame n frame All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 ...
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... NXP Semiconductors bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 Fig 7. DDRAM to display data mapping 8.1 Addressing Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 9 addressed by the address pointer. The address ranges are 127 (7Fh) and (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see (Y = 4), Y wraps around to 0 and X increments to address the next column ...
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... NXP Semiconductors row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address ( and Y = 0). The Y address 5 is reserved for icon data and is not affected by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM ...
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... NXP Semiconductors 9. Instructions Only two PCF8531 registers, the instruction register and the data register can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is ...
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... NXP Semiconductors 9.2 Function set 9.2.1 PD When the power-down mode of the LCD driver is active: • All LCD outputs at V • Power-On Reset (POR) detection active, oscillator off • V LCD • C-bus is operational, commands can be executed • RAM contents not cleared; RAM data can be written • ...
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... NXP Semiconductors 9.7 Set bias system The bias voltage levels are set in the ratio of R − R − n × R − R − R (see Fig 11. Voltage divider chain Different multiplex rates require different bias settings. Bias settings are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by: ...
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... NXP Semiconductors 9.8 LCD bias voltage Table 9. Symbol 9.9 Set V LCD V can be set by software. The voltage at intersection temperature [V LCD be calculated as: V The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at intersection temperature ( LCD The parameter values are given in ...
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... NXP Semiconductors Table 10. Symbol T ints a b programming range V LCD VOP[6:0] (programmed) [00h to 7Fh] program range LOW to HIGH Fig 12. V programming of PCF8531 LCD 9.10 Voltage multiplier control S[1:0] The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal or external), the voltage multiplier is set to 2 × setting bits S[1:0] (see 9 ...
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... NXP Semiconductors Fig 13. V Linear temperature compensation is supported in the PCF8531. The temperature coefficient of V Table 13). Table 11. Instruction set 2 Instruction I C-bus command RS R/W H1 and H0 = don’t care (H independent command page) NOP 0 0 write data 1 0 set default H[1: and (function and RAM command page) ...
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... NXP Semiconductors Table 11. Instruction set …continued 2 Instruction I C-bus command RS R/W temperature control 0 0 test modes control 0 0 LCD [1] R/W is set to the slave address byte; Co and RS are set in the control byte. Table 12. Bit H[1:0] D and E HVE PRS TC[2:0] S[1:0] [1] The bits H[1:0] identify the command page (use set default H[1:0] command to set H[1:0] = 0). ...
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... NXP Semiconductors Table 13. Bits TC[2:0] Voltage multiplier factor (S) S[1:0] PCF8531 Product data sheet Description of bits H, D and E, TC and S Value 000 001 010 011 100 101 110 111 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 PCF8531 34 x 128 pixel matrix driver … ...
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... NXP Semiconductors 2 10. I C-bus interface 10.1 Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy ...
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... NXP Semiconductors • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed and the message is not corrupted • ...
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... NXP Semiconductors Fig 17. Acknowledge on the I 2 10.2 I C-bus protocol This driver does not support read. The PCF8531 is a slave receiver. Therefore, it only responds when R the slave address byte. Before any data is transmitted on the I first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531. ...
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... NXP Semiconductors S Fig 18. Slave address and control byte acknowledge from PCF8531 slave address R/W Co Fig 19. Master transmits to slave receiver; write mode 10.3 Command decoder The command decoder identifies command words that arrive on the I significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow ...
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... NXP Semiconductors 11. Internal circuitry PADS DD1 V SS1 PADS PADS SS2 V SS1 V DD1 PADS 73, 74, 50, 51, 52 SCL, SDA, SDACK V SS1 V DD1 PADS 15, 54, 71, 72, 56, 31, 55 OSC, SA0, T3, T1, T4, RES, ENR V SS1 For all diagrams the maximum forward current and the maximum reverse voltage ...
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... NXP Semiconductors 12. Limiting values Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD1 V DD2 V DD3 V LCD DD(LCD tot P/out V ESD stg T amb [1] Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages are referenced to V [2] Pass level ...
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... NXP Semiconductors 13. Static characteristics Table 15. Static characteristics V = 1 DD1 DD2 − ° ° +85 C; unless otherwise specified. amb Symbol Parameter Supplies V LCD supply voltage LCD V supply voltage 1 DD1 V supply voltage 2 DD2 V supply voltage 3 DD3 I supply current DD I LCD supply current ...
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... NXP Semiconductors [1] As the programming range for the internally generated V while setting the VOP register and selecting the temperature compensation, that the V under all conditions and including all tolerances. [2] LCD outputs are open circuit, inputs 7.0 V; voltage multiplier = 3 × DD1 ...
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... NXP Semiconductors V DD RES Fig 21. Reset timing SDA t BUF SCL SDA 2 Fig 22. I C-bus timing PCF8531 Product data sheet t su(RESL) t LOW t HD;STA HD;DAT t SU;STA All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 PCF8531 34 x 128 pixel matrix driver ...
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... NXP Semiconductors 400 I DD (μA) 300 200 LCD 7.5 V 100 × voltage multiplier DD1 BS = 100 load. LCD Fig 23. Supply current as a function of supply voltage 2 and supply voltage LCD ( − 7 LCD DD1 DD3 no V load. LCD Fig 25. LCD supply voltage as a function of ...
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... NXP Semiconductors 30 I (μA) I DD(LCD 2 and V DD1 DD2 = 27 ° 100 amb Fig 27. Supply current as a function of frequency PCF8531 Product data sheet mgs481 (kHz) = 2.5 V; external V ; DD3 LCD load. LCD Fig 28. Supply current as a function of LCD supply All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 15. Application information 15.1 Typical system configuration DD1 DD3 V DD(I2C RES SCL SDA SS1 SS2 Fig 29. Typical system configuration The host microprocessor/microcontroller and the PCF8531 are both connected to the 2 I C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors ...
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... NXP Semiconductors Fig 31. Recommended V 15.3 Power supply connections for external V 1 5.5 V Fig 32. Recommended V 15.4 Information about V V LCDIN the bias level buffers. V LCDOUT charge pump. In this case pin V (see Figure source (see V LCDSENSE V LCDOUT connected to V PCF8531 Product data sheet 1 μ ...
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... NXP Semiconductors 15.5 Chip-on-glass application Fig 33. Chip-on-glass application The required minimum values for the external capacitors in a chip-on-glass application are: • C ext and V • Higher capacitor values are recommended for ripple reduction. • For COG applications, the recommended ITO track resistance must be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ω ...
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... NXP Semiconductors 15.6 Programming example Table 17. Programming example for PCF8531 Step Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PCF8531 Product data sheet SA0 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 34 x 128 pixel matrix driver ...
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... NXP Semiconductors Table 17. Programming example for PCF8531 Step Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PCF8531 Product data sheet …continued SA0 0 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 34 x 128 pixel matrix driver ...
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... NXP Semiconductors Table 17. Programming example for PCF8531 Step Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PCF8531 Product data sheet …continued All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 34 x 128 pixel matrix driver ...
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... NXP Semiconductors 16. Package outline Not applicable. 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. ...
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... NXP Semiconductors Fig 35. Tray alignment 19. Abbreviations Table 19. Acronym CDM CMOS COG DDRAM EMC ESD HBM HV IC ITO LCD LSB MM MPU POR RAM RC TC SCL SDA PCF8531 Product data sheet PCF8531 The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray ...
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... NXP Semiconductors 20. References [1] AN10706 — Handling bare die [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [5] JESD22-A115 — ...
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... NXP Semiconductors 21. Revision history Table 20. Revision history Document ID Release date PCF8531 v.5 20100810 • Modifications: Added • Added • Changes and corrections in • Deleted old fab information PCF8531_4 20080613 PCF8531_3 20000211 PCF8531_2 19990810 PCF8531_SDS_1 19990322 PCF8531 Product data sheet Data sheet status ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 Oscillator 7.2 Power-On Reset (POR 7.3 I C-bus controller . . . . . . . . . . . . . . . . . . . . . . 14 7.4 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 Display data RAM ...