OM6290 NXP Semiconductors, OM6290 Datasheet - Page 14
![DEMO BOARD LCD GRAPHIC DRIVER](/photos/9/4/90479/om6290_sml.jpg)
OM6290
Manufacturer Part Number
OM6290
Description
DEMO BOARD LCD GRAPHIC DRIVER
Manufacturer
NXP Semiconductors
Datasheets
1.PCF8576T1118.pdf
(44 pages)
2.OM6290.pdf
(30 pages)
3.OM6290.pdf
(51 pages)
4.OM6290.pdf
(83 pages)
Specifications of OM6290
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16/32-Bit
Utilized Ic / Part
PCF2119, PCF8531, PCF8576
Primary Attributes
Character, Graphic and Segment LCD Drivers
Secondary Attributes
JTAG, I²C, UART & USB Interfaces
Description/function
Demo Board
Interface Type
USB, I2C, JTAG, UART
Data Bus Width
4 bit, 8 bit, 16 bit
Operating Voltage
1.8 V to 5.5 V
For Use With/related Products
PCF8576DT, PCF2119S, PCF8531
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4703
NXP Semiconductors
7. Functional description
PCF8531
Product data sheet
7.1 Oscillator
7.2 Power-On Reset (POR)
7.3 I
7.4 Input filters
7.5 Display data RAM
7.6 Timing generator
7.7 Address counter
7.8 Display address counter
7.9 Command decoder
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC input must be connected to V
signal, if used, is connected to this input.
The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure.
The I
I
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
The PCF8531 contains 34 × 128 bits static RAM for storing the display data, see
The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 5 is used for icon
data. During RAM access, data is transferred to the RAM via the I
is a direct correspondence between the X address and column output number.
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not affected by operations on the data buses.
The address counter sets the addresses of the display data RAM for writing.
The display address counter generates the addresses for read out of the display data.
The command decoder identifies command words that arrive on the I
determines the destination for the following data bytes.
2
2
C-bus slave receiver and therefore it cannot control bus communication.
C-bus controller
2
C-bus controller receives and executes the commands. The PCF8531 acts as an
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 10 August 2010
34 x 128 pixel matrix driver
2
C-bus interface. There
DD
2
C-bus and
PCF8531
. An external clock
© NXP B.V. 2010. All rights reserved.
Figure
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7.