OM6290 NXP Semiconductors, OM6290 Datasheet
OM6290
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OM6290 Summary of contents
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PCF2119x LCD controllers/drivers Rev. 9 — 14 April 2011 1. General description The PCF2119x is a low power CMOS matrix LCD display of 2-lines by 16 characters or 1-line by 32 characters with 5 × 8 dot format. All necessary ...
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... NXP Semiconductors Uses common 11 code instruction set (extended) Logic supply voltage: V battery cells) LCD supply voltage LCD V DD3 Direct mode to save current consumption for icon mode and multiplex drive mode 1:9 (depending on V Very low current consumption (20 μA to 200 μA): Icon mode: < 25 μA Power-down mode: < ...
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... NXP Semiconductors 5. Marking Table 2. Type number PCF2119AU/2DA/2 PCF2119DU/2/2 PCF2119FU/2/F2 PCF2119IU/2DA/2 PCF2119RU/2/F2 PCF2119RU/2DB/2 PCF2119SU/2/F2 PCF2119X Product data sheet Marking codes All information provided in this document is subject to legal disclaimers. Rev. 9 — 14 April 2011 PCF2119x LCD controllers/drivers Marking code PC2119-2 PC2119-2 PC2119-2 PC2119-2 PC2119-2 ...
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... NXP Semiconductors 6. Block diagram BIAS VOLTAGE LCDIN GENERATOR LCDOUT V LCD 36 GENERATOR V LCDSENSE DD1 DD2 DD3 SS1 SS2 153 T3 DATA REGISTER (DR) 8 163 DB3/SA0 160 to 162 DB0 to DB2 Fig 1. Block diagram of PCF2119x PCF2119X Product data sheet C1 to C80 60 to 99, 101 to 140 80 COLUMN DRIVERS ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. PCF2119X Product data sheet dummy R17 C80 60 C66 74 C65 75 C41 R17DUP 100 C40 C16 125 C15 126 C1 R18 R9 142 R16 149 dummy 150 Viewed from active side. For mechanical details, see Pinning diagram of PCF2119x (bare die) All information provided in this document is subject to legal disclaimers. Rev. 9 — ...
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... NXP Semiconductors 7.2 Pin description Table 3. Symbol V DD1 V DD2 V DD3 E T1 and T2 V SS1 V SS2 V LCDSENSE V LCDOUT V LCDIN dummy R8 to R1, R17, R17DUP, R18 R16 C80 to C41, C40 to C1 dummy SCL T3 POR PCF2119X Product data sheet Pin description Pin Description supply voltage 1 (logic) ...
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... NXP Semiconductors Table 3. Symbol PD SDA R/W RS DB0 to DB2, DB3/SA0, DB4 to DB7 OSC [1] Always put V [2] When the I [3] The substrate (rear side of the die) is wired to V [4] On the device connected to V [5] When the parallel bus is used, the pins SCL and SDA must be connected to V left open-circuit ...
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... NXP Semiconductors 8. Functional description 8.1 Oscillator and timing generator The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency f which equals either the built in oscillator frequency f clk f . clk(ext) 8.1.1 Timing generator The timing generator produces the various signals required to drive the internal circuitry. ...
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... NXP Semiconductors Table 4. State after reset Step Function 1 Clear_display 2 Entry_mode_set 3 Display_ctl 4 Function_set 5 default address pointer to DDRAM 6 Icon_ctl 7 Screen_conf Disp_conf 8 Temp_ctl 9 VLCD_set C-bus interface reset 11 HV_gen [1] The Busy Flag (BF) indicates the busy state (bit until initialization ends. The busy state lasts 2 ms. The chip may also be ...
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... NXP Semiconductors 8.4 LCD supply voltage generator The LCD supply voltage may be generated on-chip. The V two internal 6-bit registers: V character mode and register V The nominal LCD operating voltage at room temperature is given LCD nom Where V It should be noted that V 8.4.1 Programming ranges Possible values for V Table 5 ...
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... NXP Semiconductors Remarks: • Values producing more than 6 operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage, the temperature coefficient of V • Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed ...
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... NXP Semiconductors Table 6. Bias levels as a function of multiplex rate Multiplex Number of Bias voltages rate bias levels LCD 1 LCD 1 LCD The RMS on-state voltage (V RMS off-state voltage ( RMS V ( off RMS where the values of a are for for and the values for n are ...
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... NXP Semiconductors V on(RMS (see V and V low manufacturer important to match the module properties to those of the driver in order to achieve optimum performance. Fig 3. 8.6 LCD row and column drivers The PCF2119x contains 18 row and 80 column drivers, which drive the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows ...
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... NXP Semiconductors frame n V LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 COL LCD V 2 COL LCD 0.5V LCD state 1 0.25V LCD 0 −0.25V LCD −0.5V LCD −V LCD V LCD ...
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... NXP Semiconductors frame n V LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 ROW LCD V 2 COL LCD V 2 COL LCD 0.5V LCD state 1 0.25V LCD 0 −0.25V LCD −0.5V LCD −V LCD V LCD 0.5V LCD state 2 ...
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... NXP Semiconductors V LCD 2/3 ROW 17 1 LCD 2/3 ROW 18 1 LCD 2/3 ROW 1 LCD 2/3 COL 1 ON/OFF 1 LCD 2/3 COL 2 ON/OFF 1 LCD 2/3 COL 3 ON/OFF 1 LCD 2/3 COL 4 ON/OFF 1 LCD 0.66V LCD 0.33V LCD state 1 0 −0.33V LCD −0.66V LCD −V ...
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... NXP Semiconductors 9. Display data RAM and ROM 9.1 DDRAM The Display Data RAM (DDRAM) stores characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in With no display shift the characters represented by the codes in the first 32 RAM locations starting at address 00h are displayed in line 1 ...
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... NXP Semiconductors Fig 9. When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits 1 xxxx 0000 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits 1 xxxx 0000 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits 1 xxxx 0000 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits 1 xxxx 0000 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits 1 xxxx 0000 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. ...
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... NXP Semiconductors upper 4 bits 0000 0001 lower 4 bits xxxx 0000 1 xxxx 0001 2 3 xxxx 0010 4 xxxx 0011 5 xxxx 0100 6 xxxx 0101 7 xxxx 0110 8 xxxx 0111 9 xxxx 1000 xxxx 1001 10 11 xxxx 1010 12 xxxx 1011 13 xxxx 1100 14 xxxx 1101 15 xxxx 1110 16 xxxx 1111 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM ...
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... NXP Semiconductors 9.3 CGRAM user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see • 6 CGRAM characters if icons blink and both icon rows are used in the application • 3 CGRAM characters if no icons blink but both icon rows are used in the application • ...
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... NXP Semiconductors 9.4 Cursor control circuit The cursor control circuit generates the cursor underline and/or cursor blink as shown in Figure 17 Fig 17. Cursor and blink display examples Fig 18. Example of displays with icons PCF2119X Product data sheet at the DDRAM address contained in the address counter. ...
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... NXP Semiconductors 10. Registers The PCF2119x has two 8-bit registers, an instruction register and a data register. Only these two registers can be directly controlled by the microcontroller. Before an internal operation, the control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs ...
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... NXP Semiconductors The RS bit determines which register will be accessed and the R/W bit indicates read or a write operation (see Table 10. Symbol RS R/W [1] There is only write access to the instruction register, but read access to the busy flag (BF) and the address counter (AC) of the BF_AC instruction (see [2] Write and read access ...
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... NXP Semiconductors Table 11. Instruction register overview [1] Instruction Bits RS R/W Basic instructions (bit [3] NOP 0 0 Function_set 0 0 BF_AC 0 1 Read_data 1 1 Write_data 1 0 Standard instructions (bit Clear_display 0 0 Return_home 0 0 Entry_mode_set 0 0 Display_ctl 0 0 Curs_disp_shift 0 0 Set_CGRAM 0 0 Set_DDRAM 0 0 Extended instructions (bit ...
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... NXP Semiconductors 10.2.1 Basic instructions (bit 10.2.1.1 Function_set Table 12. Bit RS R [1] When 4-bit width is selected, data is transmitted in two cycles using the parallel-bus 4-bit application ports DB3 to DB0 should be left open-circuit (internal pull-ups). [2] Default value after power- [3] No impact [4] Due to the internal pull-ups on DB3 to DB0 in a 4-bit application, the first Function_set after power-on sets bits M, SL and H to logic 1 ...
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... NXP Semiconductors Busy flag: The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit and bit R Instructions should only be started after checking that the busy flag is at logic 0 or after waiting for the required number of cycles. ...
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... NXP Semiconductors The previous Set_CGRAM or Set_DDRAM command determines if data is written into CGRAM or DDRAM. After writing, the address counter automatically increments or decrements accordance with the Entry_mode_set (see 4 to bit 0 of CGRAM data are valid, bit 7 to bit 5 are ‘don’t care’. ...
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... NXP Semiconductors 10.2.2.3 Entry_mode_set Table 18. Bit RS R Bit I_D: When bit I_D = 1 the DDRAM or CGRAM address increments by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right. When bit I_D = 0 the DDRAM or CGRAM address decrements by 1 when data is written into or read from the DDRAM or CGRAM ...
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... NXP Semiconductors Bit D: The display is on when bit and off when bit Display data in the DDRAM is not affected and can be displayed immediately by setting bit When the display is off (bit the chip is in partial power-down mode: • The LCD outputs are connected to V • ...
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... NXP Semiconductors Bits SC and RL: Curs_disp_shift moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time ...
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... NXP Semiconductors 10.2.3 Extended instructions (bit 10.2.3.1 Screen_conf Table 23. Bit RS R Screen_conf: • If bit then the two halves of a split screen are connected in a standard way i.e. column 1/81, 2/82 to 80/160. • If bit then the two halves of a split screen are connected in a mirrored way i.e. ...
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... NXP Semiconductors Fig 19. Use of bit P Bit Q: The Q bit flips the display top to bottom by mirroring the row data, as shown in Figure 20. Fig 20. Use of bit Q Combination of bit P and bit Q: A combination of P and Q allows the display to be rotated horizontally and vertically by 180 degree, as shown in viewing the display from the opposite edge ...
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... NXP Semiconductors 10.2.3.3 Icon_ctl Table 25. Bit RS R The PCF2119x can drive up to 160 icons. See icon mapping. Bit IM: When bit the chip is in character mode. In the character mode characters and icons are driven (multiplex drive mode 1:18 or 1:9). The V produces the V When bit the chip is in icon mode ...
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... NXP Semiconductors Table 27. Parameter cursor character blink block (all on) icons Fig 22. CGRAM to icon mapping (a) icon no. phase ROW/COL 1-5 even 17/1-5 6-10 even 17/6-10 11-15 even 17/11-15 76-80 even 17/76-80 81-85 even 18/1-5 156-160 even 18/76-80 1-5 odd (blink) 17/1-5 156-160 odd (blink) 18/76-80 CGRAM data: logic data bit turns the icon on and logic 0 turns the icon off ...
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... NXP Semiconductors Remark: In direct mode, no external V The direct mode can be used to reduce the current consumption when the required output voltage V in MUX 1:9 (depending on LCD liquid properties). 10.2.3.4 Temp_ctl Table 28. Bit RS R The bit-field TC[1:0] selects the temperature coefficient for the internally generated ...
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... NXP Semiconductors 10.2.3.6 VLCD_set Table 32. Bit RS R The V LCD programmed by instruction. Two on-chip registers (V factor for the character mode and the icon mode, respectively. The generated V value is independent programming Send Function_set instruction with bit Send VLCD_set instruction to write to the voltage register: a ...
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... NXP Semiconductors 11. Basic architecture 11.1 Parallel interface The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 ports DB7 to DB0. Three further control lines E, RS and R/W are required. ...
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... NXP Semiconductors RS R/W E internal DB7 Fig 25. An example of 4-bit data transfer timing sequence RS R/W E internal data DB7 instruction write Fig 26. Example of busy flag checking timing sequence PCF2119X Product data sheet internal operation IR7 IR3 busy instruction busy flag write check IR7, IR3: instruction 7th, 3rd bit. ...
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... NXP Semiconductors 2 11.2 I C-bus interface 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial DAta line (SDA) and the Serial CLock line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy ...
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... NXP Semiconductors Fig 30. Acknowledgement on the I 2 11.2.1 I C-bus protocol 2 Two I C-bus slave addresses (0111 010 and 0111 011) are reserved for the PCF2119x.The entire I Table 33. Bit Bit 1 of the slave address byte, that a PCF2119x will respond to, is defined by the level tied to its SA0 input (V Before any data is transmitted on the I addressed first ...
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... NXP Semiconductors • Arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed and the message is not corrupted. • Synchronization: procedure to synchronize the clock signals of two or more devices. acknowledgement from PCF2119x slave address R/W Co Fig 31. Master transmits to slave receiver; write mode ...
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... NXP Semiconductors Fig 33. Master reads slave immediately after first byte; read mode (RS previously PCF2119X Product data sheet acknowledgement from PCF2119x S SLAVE S A DATA BYTE 1 A ADDRESS 0 R/W Co defined) All information provided in this document is subject to legal disclaimers. Rev. 9 — 14 April 2011 PCF2119x ...
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... NXP Semiconductors 12. Internal circuitry Table 34. Symbol V DD1 V DD2 V DD3 V SS1 V SS2 V LCDSENSE V LCDIN V LCDOUT SCL SDA OSC PD POR R/W DB0 to DB7 R1 to R18 C1 to C80 PCF2119X Product data sheet Device protection circuits Pin 151 to 152 156 to 157 168 155 154 20 21 ...
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... NXP Semiconductors 13. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD1 V DD2 V DD3 V LCD DD(LCD) P tot ESD stg T amb [1] Pass level; Human Body Model (HBM) according to [2] Pass level; Machine Model (MM), according to [3] Pass level; latch-up testing according to ...
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... NXP Semiconductors 14. Static characteristics Table 36. Static characteristics DD1 DD2 DD3 unless otherwise specified. Symbol Parameter Supplies V supply voltage 1 DD1 V supply voltage 2 DD2 V supply voltage 3 DD3 V LCD supply voltage LCD Ground supply current using external V I ground supply current SS Ground supply current using internal V ...
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... NXP Semiconductors Table 36. Static characteristics DD1 DD2 DD3 unless otherwise specified. Symbol Parameter C input capacitance i Output: pin SDA I LOW-level output current output sink current OL LCD outputs R output resistance O ΔV bias voltage variation bias ΔV LCD voltage variation LCD [1] LCD outputs are open-circuit; inputs ° ...
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... NXP Semiconductors 15. Dynamic characteristics Table 37. Dynamic characteristics DD1 DD2 DD3 otherwise specified. Symbol Parameter Clock and oscillator f LCD frame frequency fr(LCD) f oscillator frequency osc f external oscillator frequency osc(ext) t start-up delay time on pin OSC oscillator, after power-down d(startup)(OSC) Timing characteristics of parallel interface Write operation (writing data from microcontroller to PCF2119x) ...
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... NXP Semiconductors Table 37. Dynamic characteristics DD1 DD2 DD3 otherwise specified. Symbol Parameter t set-up time for STOP condition SU;STO t pulse width of spikes that must SP be suppressed by the input filter t bus free time between a STOP BUF and START condition [1] Tested on sample base. ...
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... NXP Semiconductors SDA SCL SDA Fig 36. I PCF2119X Product data sheet t t BUF LOW t HD;STA C-bus timing diagram All information provided in this document is subject to legal disclaimers. Rev. 9 — 14 April 2011 PCF2119x LCD controllers/drivers HD;DAT t HIGH t SU;STA © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 16. Application information 16.1 General application information The required minimum value for the external capacitors in an application with the PCF2119x are: C Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ω ...
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... NXP Semiconductors 16.3 Power supply connections for external V Fig 39. Recommended V Fig 40. Recommended V Remark: When using an external V switched on and direct mode must be avoided otherwise damages will occur. 16.4 Information about V V LCDIN the bias level buffers. V LCDOUT must be connected to V must be left unconnected. ...
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... NXP Semiconductors Table 38. Original mode character mode display on V generator operating LCD any mode 16.6 Charge pump characteristics Typical graphs of the total power consumption of the PCF2119x using the internal charge pump are illustrated in The graphs were obtained under the following conditions: • ...
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... NXP Semiconductors (μA) (1) 2 × multiplication factor. (2) 3 × multiplication factor. (3) 4 × multiplication factor. Fig 42. Typical charge pump characteristics (b), V (μA) (1) 2 × multiplication factor. (2) 3 × multiplication factor. (3) 4 × multiplication factor. Fig 43. Typical charge pump characteristics (c), V PCF2119X ...
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... NXP Semiconductors 16.7 Interfaces Fig 44. Typical application using parallel interface bit bus possible Fig 45. Application using I PCF2119X Product data sheet OSC PCF2119X 470 V LCD nF 100 4,8 DB7 to DB4 E DB3 to DB0 OSC PCF2119X 470 V LCD nF 100 OSC PCF2119X 470 V LCD nF 100 SCL SDA ...
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... NXP Semiconductors 16.8 Connections with LCD modules Fig 46. Connecting PCF2119x with 2 × 16 character LCD R17 PCF2119X C1 to C80 R9 to R16 R18 Fig 47. Connecting PCF2119x with 1 × 32 character LCD PCF2119X Product data sheet R17 PCF2119X C1 to C80 R16 8 R18 Icons 8 Character row 1 ...
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... NXP Semiconductors 16.9 4-bit operation, 1-line display using external reset The program must set functions prior to a 4-bit operation (see turned on, 8-bit operation is automatically selected and the PCF2119x attempts to perform the first write as an 8-bit operation. Since nothing is connected to ports DB0 to DB3, a rewrite is then required ...
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... NXP Semiconductors Table 40. 8-bit operation, 1-line display example; using external reset (character set ‘A’) Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 4 Entry_mode_set Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM Entry_mode_set Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM Curs_disp_shift ...
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... NXP Semiconductors Table 41. 8-bit operation, 1-line display and icon example; using external reset (character set ‘A’) Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 power supply on 2 Function_set Display_ctl Entry_mode_set Set_CGRAM Write_data to CGRAM/DDRAM Set_CGRAM Write_data to CGRAM/DDRAM Function_set ...
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... NXP Semiconductors 16.11 8-bit operation, 2-line display For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed ...
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... NXP Semiconductors Table 42. 8-bit operation, 2-line display example; using external reset (character set ‘A’) Instruction Step RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display 22 23 Return_home 16.12 I C-bus operation, 1-line display A control byte is required with most commands (see 2 Table 43 ...
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... NXP Semiconductors 2 Table 43. Example of I C-bus operation; 1-line display (using external reset, assuming pin SA0 = V 2 Step I C-bus byte 16 Write_data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS optional l C-bus STOP C-bus start 19 slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS ...
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... NXP Semiconductors 16.13 Initialization Table 44. Initialization by instruction, 8-bit interface ( Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 power-on or unknown state 2 wait Function_set wait Function_set wait more than 40 μ Function_set can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the ...
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... NXP Semiconductors Table 45. Step can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see PCF2119X Product data sheet Initialization by instruction, 4-bit interface; not applicable for I Instruction RS R/W DB7 DB6 DB5 DB4 ...
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... NXP Semiconductors 16.14 User defined characters and symbols user defined characters may be stored in the CGRAM. The content of the CGRAM is lost during power-down, therefore the CGRAM has to be rewritten after every power-on. Fig 48. User defined euro currency sign Below some source code is printed, which shows how a user defined character is defined - in this case the euro currency sign ...
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... NXP Semiconductors i2c_write(0x06); // 00110 i2c_stop(); // Until here the definition of the character and writing it into the CGRAM. Now it // still needs to be displayed. See below. // PCF2119, setting of proper display modes startI2C(); // PCF2119 slave address for write, SA0 is connected to Vdd SendI2CAddress(0x76); // MSB (Continuation bit Co more than one byte may follow. Bit6, RS=0, next byte // is command byte i2c_write(0x00) ...
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... NXP Semiconductors 17. Bare die outline Bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm PC2119 detail X 0 Dimensions (1) (1) (1) Unit max 0.0225 mm nom 0.380 0.0175 0.050 0.100 min 0.0125 Note 1. Dimension not drawn to scale Outline version IEC PCF2119X Fig 49. Bare die outline of PCF2119x ...
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... NXP Semiconductors Table 46. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol V DD1 V DD1 V DD1 V DD1 V DD1 V DD1 V DD2 V DD2 V DD2 V DD2 V DD2 V DD2 V DD2 V DD2 V DD3 V DD3 V DD3 V DD3 SS1 V SS1 V SS1 V SS1 V SS1 V SS1 V SS1 V SS1 V SS2 ...
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... NXP Semiconductors Table 46. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol V LCDOUT V LCDOUT V LCDOUT V LCDIN V LCDIN V LCDIN V LCDIN V LCDIN V LCDIN dummy ( R17 C80 C79 C78 C77 C76 C75 C74 C73 C72 C71 C70 C69 C68 C67 C66 C65 ...
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... NXP Semiconductors Table 46. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 R17DUP C40 C39 C38 C37 C36 C35 C34 ...
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... NXP Semiconductors Table 46. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 R18 R9 R10 R11 R12 R13 R14 R15 R16 dummy (V SCL SCL T3 POR PD SDA SDA R/W RS DB0 ...
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... NXP Semiconductors Table 46. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol DB1 DB2 DB3/SA0 DB4 DB5 DB6 DB7 OSC Table 47. All X and Y coordinates are referenced to the center of the chip (dimensions in Symbol AM1 AM2 AM3 AM4 18. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling ...
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... NXP Semiconductors 19. Packing information Fig 50. Tray details Table 48. Dimension PCF2119X Product data sheet 1.1 2.1 3.1 1.2 2.2 1 For dimensions see Table 48. Tray has pockets on both, front side and back side. Tray dimensions Description pocket pitch x direction pocket pitch y direction ...
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... NXP Semiconductors Fig 51. Tray alignment PCF2119X Product data sheet The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pin location diagram for the orientating and position of the type name on the die surface. ...
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... NXP Semiconductors 20. Abbreviations Table 49. Acronym CGRAM CGROM CMOS COG DC DDRAM HBM ITO LCD LSB MM MSB MUX PCB POR RAM RMS ROM SCL SDA PCF2119X Product data sheet Abbreviations Description Character Generator RAM Character Generator ROM Complementary Metal-Oxide Semiconductor Chip-On-Glass Direct Current ...
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... NXP Semiconductors 21. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10706 — Handling bare die [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] JESD22-A114 — ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 Oscillator and timing generator 8.1.1 Timing generator 8.1.2 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 ...