OM6290 NXP Semiconductors, OM6290 Datasheet - Page 44
![DEMO BOARD LCD GRAPHIC DRIVER](/photos/9/4/90479/om6290_sml.jpg)
OM6290
Manufacturer Part Number
OM6290
Description
DEMO BOARD LCD GRAPHIC DRIVER
Manufacturer
NXP Semiconductors
Datasheets
1.PCF8576T1118.pdf
(44 pages)
2.OM6290.pdf
(30 pages)
3.OM6290.pdf
(51 pages)
4.OM6290.pdf
(83 pages)
Specifications of OM6290
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16/32-Bit
Utilized Ic / Part
PCF2119, PCF8531, PCF8576
Primary Attributes
Character, Graphic and Segment LCD Drivers
Secondary Attributes
JTAG, I²C, UART & USB Interfaces
Description/function
Demo Board
Interface Type
USB, I2C, JTAG, UART
Data Bus Width
4 bit, 8 bit, 16 bit
Operating Voltage
1.8 V to 5.5 V
For Use With/related Products
PCF8576DT, PCF2119S, PCF8531
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4703
NXP Semiconductors
PCF2119X
Product data sheet
11.2 I
The I
The two lines are the Serial DAta line (SDA) and the Serial CLock line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
2
Fig 27. System configuration
Fig 28. Bit transfer
Fig 29. Definition of START and STOP conditions
C-bus interface
2
SCL
SDA
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
All information provided in this document is subject to legal disclaimers.
SDA
SCL
S
Rev. 9 — 14 April 2011
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
SLAVE
allowed
change
of data
TRANSMITTER
MASTER
STOP condition
LCD controllers/drivers
mbc621
P
PCF2119x
TRANSMITTER/
© NXP B.V. 2011. All rights reserved.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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