CDB4271 Cirrus Logic Inc, CDB4271 Datasheet - Page 7
CDB4271
Manufacturer Part Number
CDB4271
Description
EVAL BOARD CS4271 STEREO CODEC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CDB4271.pdf
(28 pages)
Specifications of CDB4271
Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS4271
Primary Attributes
Stereo, 24-Bit, 192 kHz Sample Rate
Secondary Attributes
I²S, S/PDIF Inputs and Outputs, Analog Inputs and Outputs, GUI
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1003
1.7
1.8
dielectric absorption properties. The HPF formed by this R-C pair must be such that the volt-
age across the aluminum electrolytic DC-block capacitor is minimal at 20 Hz. This keeps the
distortion due to the electrolytic's dielectric absorption properties to a minimum. For a design
utilizing only LPF configuration 1, there is no post-LPF resistor-divider pad, and a much
smaller value capacitor can be used (22 F).
Similar to the output DC-block capacitor described above, the value of the AC coupling
capacitor from the non-inverting input of the 2-pole low pass to ground (C23 for AOUTR) was
also chosen to minimize the rise in distortion performance at low frequency due to the elec-
trolytic's dielectric absorption properties. These properties become apparent only as the
signal level on that leg increases to the levels output from the differential amp used in LPF
configuration 2. For a design utilizing only LPF configuration 1, the levels on that leg are suf-
ficiently low, and a much smaller value capacitor can be used (22 F).
Switch S1 allows stand-alone hardware signal routing and configuration of the CDB4271.
See Table 2 for a list of the various options available. After changing settings using S1, the
user must assert a reset by pressing the RESET button (S2).
Operation in stand-alone mode requires the parallel port cable to remain disconnected from
the DB-25 connector (J31). Connecting a cable to the connector will enable the PC control
port, automatically disabling switch S1 and its associated logic.
A graphical user interface is included with the CDB4271 to allow easy manipulation of all reg-
isters of the CS4271 and hardware configuration of the CDB4271. Connecting a cable to the
DB-25 connector (J31) will enable the PC control port, automatically disabling switch S1 and
its associated logic.
Stand-Alone Control
PC Parallel Port Control
CDB4271
7