CDB42528 Cirrus Logic Inc, CDB42528 Datasheet
CDB42528
Specifications of CDB42528
Related parts for CDB42528
CDB42528 Summary of contents
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... A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42528 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42528 Customer Dem- onstration board is also available for device evaluation. Refer to TXP ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 SPECIFIED OPERATING CONDITIONS ............................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 7 ANALOG INPUT CHARACTERISTICS .................................................................................................. 8 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 9 ANALOG OUTPUT CHARACTERISTICS ............................................................................................ 10 D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ ...
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REGISTER DESCRIPTION .................................................................................................................. 46 6.1 Memory Address Pointer (MAP) ..................................................................................................... 46 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 46 6.3 Power Control (address 02h) .......................................................................................................... 47 6.4 Functional Mode (address 03h) ...................................................................................................... 48 6.5 Interface ...
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Circuit Board Layout ............................................................................................................ 80 11. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 81 11.1 AES3 Receiver External Components .......................................................................................... 81 12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 82 13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 84 14. PACKAGE ...
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Figure 42.Quad-Speed Mode Stopband Rejection ................................................................................... 83 Figure 43.Quad-Speed Mode Transition Band ......................................................................................... 83 Figure 44.Quad-Speed Mode Transition Band (Detail) ............................................................................. 83 Figure 45.Quad-Speed Mode Passband Ripple ....................................................................................... 83 Figure 46.Single-Speed (fast) Stopband Rejection ................................................................................... 84 Figure 47.Single-Speed (fast) Transition ...
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LIST OF TABLES Table 1. Common OMCK Clock Frequencies ............................................................................................ 26 Table 2. Common PLL Output Clock Frequencies..................................................................................... 26 Table 3. Slave Mode Clock Ratios ............................................................................................................. 27 Table 4. Serial Audio Port Channel Allocations ......................................................................................... 28 Table 5. DAC De-Emphasis ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25° C.) A SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, ...
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ANALOG INPUT CHARACTERISTICS (T = 25° =VARX 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Mea- A surement Bandwidth ...
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A/D DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode ( kHz sample rates) Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Double-Speed Mode (50 to 100 kHz ...
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ANALOG OUTPUT CHARACTERISTICS (T = 25° =VARX 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measure- A ment Bandwidth kHz ...
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D/A DIGITAL FILTER CHARACTERISTICS Parameter Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner corner Frequency Response kHz StopBand StopBand Attenuation Group ...
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SWITCHING CHARACTERISTICS (For CQZ -10 to +70° C; For DQZ VA=VARX = =VLC= 3.3 V, VLS = 1 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C Parameters ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For CQZ -10 to +70° C; For DQZ 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C Parameter SCL Clock Frequency RST Rising Edge to ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI (For CQZ -10 to +70° C; For DQZ 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C Parameter CCLK Clock Frequency CS High Time Between Transmissions ...
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DC ELECTRICAL CHARACTERISTICS (T = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) A Parameter Power Supply Current normal operation VARX = 5 V (Note 23) Interface current, VLC=5 V power-down state (all ...
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DIGITAL INTERFACE CHARACTERISTICS (For CQZ +25° C; For DQZ Parameters (Note 27) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Serial Port, ...
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PIN DESCRIPTIONS CX_SDIN1 1 CX_SCLK 2 CX_LRCK VLC 6 SCL/CCLK 7 SDA/CDO UT 8 AD1/CDIN 9 AD0/CS 10 INT 11 RST 12 AINR- 13 AINR+ 14 AINL+ 15 AINL- 16 Pin Name # ...
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Interrupt (Output ) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register. 11 INT See “Interrupts” on page 40 Reset ( Input ) - The device enters a low power mode and all internal registers ...
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External Reference Clock ( Input ) - External clock reference that must be within the ranges specified in 59 OMCK the register “OMCK Frequency (OMCK Freqx)” on page Serial Audio Interface Left/Right Clock ( Input / Output ) - Determines ...
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TYPICAL CONNECTION DIAGRAM + 3 0.1 µ µ F 0.1 µ µ river Interfac ources +2.5 ...
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APPLICATIONS 4.1 Overview The CS42528 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con- verters (ADC), implemented using multi-bit delta-sigma techniques, 8 digital-to-analog converters (DAC) and a 192 kHz digital audio S/PDIF receiver. Other functions ...
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High-Pass Filter and DC Offset Calibration The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high-pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set ...
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Digital Volume and Mute Control Each DAC’s output level is controlled via the Volume Control registers operating over the range -127 dB attenuation with 0.5 dB resolution. See 14h, 15h, 16h)” on page 0.125 dB at ...
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... A comprehensive buffering scheme provides read access to the channel status and user data. External components are used to terminate and isolate the incoming data cables from the CS42528. These components and required circuitry are detailed in the CDB42528. 4.4.1 8:2 S/PDIF Input Multiplexer The CS42528 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input dig- ital audio data ...
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Clock Generation The clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by ...
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OMCK System Clock Mode A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register ...
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When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device operation. In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not. The sample rate to OMCK ratios and OMCK ...
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CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CX_SDOUT SAI_SDOUT ADCIN1 ADCIN2 Table 4. Serial Audio Port Channel Allocations 28 Serial Inputs / Outputs DAC #1 left channel right channel DAC #2 One-Line Mode DAC channels 1,2,3,4,5,6 DAC #3 left channel right channel DAC ...
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Serial Audio Interface Formats The CODEC_SP and SAI_SP digital audio serial ports support five formats with varying bit depths from shown in Figures 10 isters, “Functional Mode (address 03h)” on page 48 For the diagrams ...
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CX_LRCK SAI_LRCK CX_SCLK SAI_SCLK CX_SDINx - CX_SDOUT MSB SAI_SDOUT Left-Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample Master 64, 128, 256 ...
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CX_LRCK SAI_LRCK CX_SCLK SAI_SCLK MSB LSB MSB CX_SDIN1 DAC1 20 clks DAC7 CX_SDIN4 20 clks ADC1 CX_SDOUT 20 clks SAI_SDOUT One-Line Data Mode #1, Data Valid on Rising Edge of SCLK Bits/Sample Master 128 Fs 20 128 Fs Figure 13. ...
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ADCIN1/ADCIN2 Serial Data Format The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port ...
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One-Line Mode (OLM) Configurations 4.6.4.1 OLM Config #1 One-Line Mode Configuration #1 can support channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data. This is the only configuration which ...
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OLM Config #2 This configuration will support channels of DAC data or 6 channels of ADC data and no channels of S/PDIF received data and will handle up to 20-bit samples at a sampling-frequency of 96 ...
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OLM Config #3 This One Line Mode configuration #3 will support channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 20-bit samples at a ...
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OLM Config #4 This configuration will support channels of DAC data 6 channels of ADC data and no channels of S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples ...
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OLM Config #5 This One-Line Mode configuration can support channels of DAC data 2 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency ...
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Control Port Description and Timing The control port is used to access the registers, allowing the CS42528 to be configured for the desired op- erational modes and formats. The operation of the control port may be completely asynchronous with ...
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I²C Mode In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There pin. Pins AD0 and AD1 form the two least-significant bits of ...
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Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. ...
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... FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB42528 evaluation board demonstrates the optimum lay- out and power supply arrangements. ...
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REGISTER QUICK REFERENCE Addr Function 7 ID 01h Chip_ID3 Chip_ID2 page 46 1 default Power Con- 02h PDN_RCVR1 PDN_RCVR0 trol page 47 1 default Functional 03h CODEC_FM1 CODEC_FM0 Mode page 46 0 default Interface 04h DIF1 Formats page 50 ...
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Addr Function 7 Vol. Control 0Fh A1_VOL7 A1_VOL6 A1 page 58 0 default Vol. Control 10h B1_VOL7 B1_VOL6 B1 page 58 0 default Vol. Control 11h A2_VOL7 A2_VOL6 A2 page 58 0 default Vol. Control 12h B2_VOL7 B2_VOL6 B2 page ...
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Addr Function 7 RCVR Mode 1Eh SP_SYNC Reserved Ctrl page 61 0 default RCVR Mode 1Fh Reserved TMUX2 Ctrl 2 page 63 0 default Interrupt 20h UNLOCK Reserved Status page 63 X default Interrupt 21h UNLOCKM Reserved Mask page 64 ...
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Addr Function 7 RXP3/GPO 2Dh Mode1 Mode0 3 page 69 0 default RXP2/GPO 2Eh Mode1 Mode0 2 page 69 0 default RXP1/GPO 2Fh Mode1 Mode0 1 page 69 0 default Q Subcode 30h Address3 Address2 page 71 X default Q ...
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REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Interrupt Sta- tus Register, and Q-Channel Subcode Bytes and C-bit or U-bit Data Buffer, which are read only. See the following bit definition ...
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Power Control (address 02h PDN_RCVR1 PDN_RCVR0 PDN_ADC 6.3.1 POWER DOWN RECEIVER (PDN_RCVRX) Default = Receiver and PLL in normal operational mode Receiver and PLL held in a reset state. Equivalent to setting ...
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Functional Mode (address 03h CODEC_FM1 CODEC_FM0 SAI_FM1 6.4.1 CODEC FUNCTIONAL MODE (CODEC_FMX) Default = Single-Speed Mode ( kHz sample rates Double-Speed Mode (50 to 100 kHz sample rates ...
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Receiver Mode Control (address 1Eh) register to set the appropriate sample rate. DAC_DEM reg03h[ 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM) Default = 0 Function: When enabled, de-emphasis will be automatically applied when emphasis is detected based on the ...
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Interface Formats (address 04h DIF1 DIF0 ADC_OL1 6.5.1 DIGITAL INTERFACE FORMAT (DIFX) Default = 01 Function: These bits select the digital interface format used for the CODEC Serial Port and Serial Audio Interface Port when not in ...
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SAI RIGHT-JUSTIFIED BITS (SAI_RJ16) Default = 0 Function: This bit determines how many bits to use during right-justified mode for the Serial Audio Interface Port. By default the receiver will be in RJ24 bits but can be set to ...
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FREEZE CONTROLS (FREEZE) Default = 0 Function: This function will freeze the previous output of, and allow modifications to be made to, the Volume Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh) registers without ...
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Clock Control (address 06h RMCK_DIV1 RMCK_DIV0 OMCK Freq1 6.7.1 RMCK DIVIDE (RMCK_DIVX) Default = 00 Function: Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor. RMCK_DIV1 RMCK_DIV0 6.7.2 OMCK FREQUENCY (OMCK FREQX) ...
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FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK. SW_CTRL1 SW_CTRL0 UNLOCK 6.7.5 FORCE PLL LOCK (FRC_PLL_LK) Default = 0 Function: This bit is used to enable ...
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AES FORMAT DETECTION (AES FORMATX) Default = xxx Function: The CS42528 will auto-detect the AES format of the incoming S/PDIF stream and display the infor- mation according to the following table. AES AES Format2 Format1 ...
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RCVR_CLK2 RCVR_CLK1 RCVR_CLK0 Table 14. Receiver Clock Frequency Detection 6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only PCx-7 PCx-6 PCx-5 PDx-7 PDx-6 PDx-5 6.10.1 BURST PREAMBLE ...
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The requested level-change will occur after a timeout period between 512 and 1024 sample periods (10 21 kHz sample rate) if the signal does not ...
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SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN) Default = Disabled 1 - Enabled Function: A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this feature is enabled, this mute ...
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Channel Invert (address 17h INV_B4 INV_A4 INV_B3 6.14.1 INVERT SIGNAL POLARITY (INV_XX) Default = Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels. 6.15 Mixing ...
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ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42528 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...
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ADC Left Channel Gain (address 1Ch Reserved Reserved LGAIN5 6.16.1 ADC LEFT CHANNEL GAIN (LGAINX) Default = 00h Function: The level of the left analog channel can be adjusted increments as dictated by the ...
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DE-EMPHASIS SELECT BITS (DE-EMPHX) Default = Reserved 01 - De-Emphasis for 32 kHz sample rate De-Emphasis for 44.1 kHz sample rate De-Emphasis for 48 kHz sample rate. Function: Used to specify which ...
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Receiver Mode Control 2 (address 1Fh Reserved TMUX2 TMUX1 6.19.1 TXP MULTIPLEXER (TMUXX) Default = 000 Function: Selects which of the eight receiver inputs will be mapped directly to the TXP output pin. TMUX2 ...
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PLL UNLOCK (UNLOCK) Default = 0 Function: PLL unlock status bit. This bit will go high if the PLL becomes unlocked. 6.20.2 NEW Q-SUBCODE BLOCK (QCH) Default = 0 Function: Indicates when the Q-Subcode block has changed. 6.20.3 D ...
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Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h UNLOCK1 Reserved QCH1 UNLOCK0 Reserved QCH0 Default = 00000000 Function: The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are ...
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C-DATA BUFFER CONTROL (CAM) Default = One byte mode 1 - Two byte mode Function: Sets the C-data buffer control port access mode. 6.23.4 CHANNEL SELECT (CHS) Default = 0 Function: When set to ‘0’, channel ...
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AUDIO INDICATOR (AUDIO) Default = x Function: A ‘0’ indicates that the received data is linearly coded PCM audio. A ‘1’ indicates that the received data is not linearly coded PCM audio. 6.24.4 SCMS COPYRIGHT (COPY) Default = x ...
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PLL LOCK STATUS (UNLOCK) Default = PLL locked 1 - PLL out of lock Function: Indicates the lock status of the PLL. 6.25.4 RECEIVED VALIDITY (V) Default = Data is valid and is ...
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HOLD bit mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR interrupt, and will not affect ...
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ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the left or right channel. The Functionx bits determine the operation of the pin. When configured as a GPO with the ...
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It is recommended that in this mode the remaining functional bits be set to 0. Function1 GPO, Drive High - If the pin is configured as a general-purpose output, the functional bits are ignored and the pin is ...
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PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made ...
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APPENDIX A: EXTERNAL FILTERS 8.1 ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input ...
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APPENDIX B: S/PDIF RECEIVER 9.1 Error Reporting and Hold Function The UNLOCK bit indicates whether the PLL is locked to the incoming S/PDIF data. The V bit reflects the current validity bit status. The CONF (Confidence) bit indicates the ...
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Receiver Figure 26. Channel Status Data Buffer Structure 9.2.1 Channel Status Data E Buffer Access The user can monitor the incoming Channel Status data by reading the E buffer, which is mapped into the register space of the CS42528 through ...
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Serial Copy Management System (SCMS) The CS42528 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. 9.3 ...
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C: PLL FILTER The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information to the PLL. This results in the PLL being immune to data-dependent jitter effects because the S/PDIF ...
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The external PLL component values listed in curve, take a short time to lock, and offer good output jitter performance. It should be noted that the PLL component values shown must be used with their associated locking modes as shown ...
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Jitter Attenuation Figures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range when used with the external PLL component values and locking modes as specified in The AES3 and IEC60958-4 specifications do not have ...
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Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary because their leads, and the required longer circuit board trac- es, add ...
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D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS 11.1 AES3 Receiver External Components The CS42528 AES3 receiver is designed to accept only consumer-standard interfaces. The standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector is ...
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E: ADC FILTER PLOTS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) Figure 34. Single-Speed Mode Stopband Rejection ...
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Frequency (normalized to Fs) Figure 40. Double-Speed Mode Transition Band (Detail) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 ...
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F: DAC FILTER PLOTS 100 120 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) Figure 46. Single-Speed (fast) Stopband Rejection 0.45 0.46 0.47 0.48 ...
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Frequency(normalized to Fs) Figure 52. Single-Speed (slow) Transition Band (detail 100 120 0.4 0.5 0.6 0.7 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 58. Double-Speed (slow) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 64. Quad-Speed (fast) Transition Band (detail 100 120 0.1 0.2 0.3 0.4 0.5 ...
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DIMENSIONS 64L LQFP PACKAGE DRAWING D D1 DIM MIN A --- A1 0.002 B 0.007 D 0.461 D1 0.390 E 0.461 E1 0.390 e* 0.016 L 0.018 ∝ 0.000° * Nominal pin pitch is 0.50 mm Controlling dimension is ...
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... Description 114 dB, 192 kHz CS42528 8-Ch Codec with S/PDIF Receiver CDB42528 CS42528 Evaluation Board 16.REFERENCES 1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998. ...
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HISTORY Release Date A1 December 2002 Advance Release PP1 August 2003 Preliminary Release PP2 August 2003 PP3 March 2004 Corrected error in document title. PP4 July 2004 Add lead free part numbers PP5 January 2005 F1 October 2005 Final ...
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in ...