STEVAL-ISQ002V1 STMicroelectronics, STEVAL-ISQ002V1 Datasheet - Page 116

BOARD EVAL BASED ON ST72264G1

STEVAL-ISQ002V1

Manufacturer Part Number
STEVAL-ISQ002V1
Description
BOARD EVAL BASED ON ST72264G1
Manufacturer
STMicroelectronics
Datasheets

Specifications of STEVAL-ISQ002V1

Main Purpose
Interface, PMBus
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F264
Primary Attributes
The PMBus™ Interface Using the ST7 I2C Peripheral
Secondary Attributes
Firmware in C Language
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6423

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Quantity
Price
Part Number:
STEVAL-ISQ002V1
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STMicroelectronics
Quantity:
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ST72260Gx, ST72262Gx, ST72264Gx
11.7 10-BIT A/D CONVERTER (ADC)
11.7.1 Introduction
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has 6 multiplexed analog input chan-
nels (refer to device pin out description) that allow
the peripheral to convert the analog voltage levels
from 6 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
11.7.2 Main Features
Figure 61. ADC Block Diagram
116/172
10-bit conversion
6 channels with multiplexed input
Linear successive approximation
AIN0
AINx
AIN1
f
CPU
ANALOG
MUX
EOC SPEED ADON SLOW
f
CPU,
3
ADCDRH
f
CPU
/2
,
f
CPU
ADCDRL
/4
D9
0
f
ADC
CH2
D8
The block diagram is shown in
11.7.3 Functional Description
11.7.3.1 Analog Power Supply
V
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
CH1
D7
DDA
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
0
CH0
and V
D6
DD
0
and V
D5
ADCCSR
SSA
0
D4
are the high and low level refer-
SS
0
ANALOG TO DIGITAL
pins.
D3
CONVERTER
0
D2
0
Figure
D1
61.
D0

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